TB67S128FTG TOSHIBA BiCD Integrated Circuit Silicon Monolithic TB67S128FTG CLOCK-in and Serial controlled Bipolar Stepping Motor Driver 1. Outline The TB67S128FTG is a two-phase bipolar stepping motor driver using a PWM chopper. The clock in decoder is built in. Fabricated with the BiCD process, output rating is 50 V/5.0 A (Motor supply voltage = 44 V). 2. Features P-VQFN64-0909-0.50-006 BiCD process integrated monolithic IC. Capable of controlling 1 bipolar stepping motor. Weight: 0.229 g (typ.) PWM controlled constant-current drive Low on-resistance (High + Low side = 0.25 (typ.)) MOSFET output stage. Allows full, half, quarter, 1/8, 1/16, 1/32, 1/64, 1/128 step operation. High efficiency motor current control mechanism (ADMD: Advanced Dynamic Mixed Decay) Built-in Anti-stall architecture (AGC: Active Gain Control) Built-in Sense resistor less current control architecture (ACDS: Advanced Current Detection System) High voltage and current (For specification, please refer to absolute maximum ratings and operation ranges) Multi error detect functions (Thermal shutdown (TSD), Over current (ISD), Power-on-reset (POR), motor load open (OPD)). Error detection (TSD/ISD/OPD) flag output function Built-in VCC regulator for internal circuit Chopping frequency of a motor can be adjusted by external resistance and capacitor. Small package with thermal pad TB67S128FTG: P-VQFN64-0909-0.50-006 Note: Please be careful about thermal conditions during using. 2018-2020 1 2020-12-15 Toshiba Electronic Devices & Storage Corporation TB67S128FTG 3. Pin Assignment Pin assignment in CLK mode (IF SEL pin = L) is shown in below figure. <TOP View> 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 MODE0 NC 31 MODE1 50 RS B 30 51 MODE2 RS B 52 29 CLK NC OUT B+ CW/CCW 28 53 OUT B+ 54 27 STANDBY 26 55 OUT B- ENABLE 25 RESET 56 OUT B- 24 57 OUT A- GAIN SEL 23 58 OUT A- EDG SEL TESTI 1 22 OUT A+ 59 60 21 OUT A+ TESTI 2 61 20 NC TESTI 3 62 19 RS A LO0 18 RS A LO1 63 NC MO 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: Please solder the corner pads and the rear thermal pad of the QFN package, to the GND pattern of the PCB. 2 2020-12-15 TESTO 1 NC TESTO 2 AGC TESTO 3 TORQE2 SGND TORQE1 OSCM TORQE0 CLIM0 MDT1 CLIM1 MDT0 GND FLIM BST GND VREF GND CP- IF SEL RS SEL CP+ NC CPOUT NC VCC LTH VM TEST VF VM