TB6865AFG Toshiba

TB6865AFG TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB6865AFG Qi compliant wireless power transmitter IC 1. Outline The TB6865AFG is wireless power transmitter (TX) IC for Qi low power v1.1 compliant of Wireless Power Consortium (WPC). TB6865AFG includes ARM Core Tex M3, PWM control, PreDriver ASK demodulate circuits for wiress power taransfer system. The IC includes all TX functions needed to construct a standalone wireless power system. LQFP100-P-1414-0.50G 2. Applications Mobile devices (Smartphone, tablet), Mobile accessory etc. 3. Features Cortex-M3 manufactured by ARM is used RAM : 8Kbyte Flash ROM : 128Kbyte Pre driver (Drive 4 Full Bridge circuit) / High Resolution PWM(100Hz step): 16 channels 12-bit Analog/Digital Converter(ADC) : 14 channels ASK signal input : 4 channels Input Output ports : 64 pins Large current for LED drive: 6 pins / Control for buzzer: 1 pin General-purpose serial interface(UART) : 2 channels 2 Serial bus interface(I C bus) : 1 channel 3.3V LDO Fail safe function (Over voltage detection , Over current detection, and Thermal shut down) Maximum operation frequency CPU : 20MHz PWM : 80MHz Operating voltage range Analog and pre driver : 4.5V to 14V Digital : 2.7V to 3.6V Package : LQFP100-P-1414-0.50G (14mm14mm, 0.5mm pitch) About solder ability, following conditions were confirmed (1) Solder ability (1) Use of Sn-37Pb solder Bath solder bath temperature = 230C dipping time = 5 seconds the number of times = once use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath solder bath temperature = 245C dipping time = 5 seconds the number of times = once use of R-type flux This product has a MOS structure and is sensitive to electrostatic discharge. When handling this product, ensure that the environment is protected against electrostatic discharge by using an earth strap, a conductive mat and an ionizer. Ensure also that the ambient temperature and relative humidity are maintained at reasonable levels. 1 2015-10-06 TB6865AFG 4. Block Diagram PVDD LDO TEST VDD33 (3.3V) VSS 8 8 8 HDRV1 to 4 Level Shifter Analog Control Circuit LDRV1 to 4 DVSS AVSS 8 8 8 HDRV5 to 8 Level Shifter RVSS LDRV5 to 8 VIN1 LDO Demodulator NGD1 (VCC1-4.5V) VIN2 VIN3 LDO Demodulator NGD2 VIN4 (VCC2-4.5V) IIN1 Demodulator FTEST3 IIN2 Cortex-M3 MCU SDA (PF0) IIN3 CPU Demodulator SCL (PF1) IIN4 4 Figure 4.1 Block Diagram 2 2015-10-06 VDD33 XT1 RVDD3 XT2 DVDD3 X1 AVDD3 X2 XRESET VREFH MODE PGND2 PGND1 PA0 to 6 PC0 to 6 PD0 to 6 PE0 to 6 PG0 to 5 PH0 to 5 PI0 to 5 VCC1 VCC2