TC74HC4538AP/AF/AFT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC4538AP, TC74HC4538AF, TC74HC4538AFT Dual Retriggerable Monostable Multivibrator The TC74HC4538A is a high speed CMOS MONOSTABLE 2 MULTIVIBRATOR fabricated with silicon gate C MOS TC74HC4538AP technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. There are two trigger inputs, A input (positive edge input), and B input (negative edge input). These inputs are valid for a slow rise/fall time signal (t = t = 1 s) as they are schmitt trigger r f inputs. After triggering, the output stays in a MONOSTABLE state for the time period determined by the external resistor and capacitor (R , C ). A low level at CD input breaks this STABLE STATE. TC74HC4538AF X X In the MONOSTABLE state, if a new trigger is applied, it makes the MONOSTABLE period longer (retrigger mode). Limitations for C and R are as follows: X X External capacitor C ........... No limitation X External resistor R .............. V = 2.0 V more than 5 k X CC V 3.0 V more than 1 k CC All inputs are equipped with protection circuits against static discharge or transient excess voltage. TC74HC4538AFT Features (Note) High speed: t = 25 ns (typ.) at V = 5 V pd CC Low power dissipation Stand by state: I = 4 A (max) at Ta = 25C CC Active state: I = 300 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Output drive capability: 10 LSTTL loads Symmetrical output impedance: I = I = 4 mA (min) OH OL Weight Balanced propagation delays: t t DIP16-P-300-2.54A : 1.00 g (typ.) pLH pHL SOP16-P-300.1.27A : 0.18 g (typ.) Wide operating voltage range: V (opr) = 2 V to 6 V CC TSSOP16-P-0044-0.65A : 0.06 g (typ.) Pin and function compatible with 4538B Note: In the case of using only one circuit, CD should be tied to GND, T1T2Q Q should be tied to OPEN, the other inputs should be tied to V or GND. CC Start of commercial production 1987-11 1 2016-12-02 TC74HC4538AP/AF/AFT Pin Assignment IEC Logic Symbol (4) & 1A 1T1 1 16 V CC (5) (6) 1B 1Q (3) 1T2 2 15 2T1 1CD R (1) (7) 1T1 C 1Q X 14 2T2 1CD 3 (2) 1T2 R /C X X 1A 4 13 2CD (12) 2A & (11) (10) 2B 2Q 5 12 2A 1B (13) 2CD R (15) (9) 1Q 6 11 2B 2T1 2Q C X (14) 2T2 R /C X X 7 10 2Q 1Q GND 8 9 2Q (top view) Truth Table Inputs Outputs Note A B CD Q Q H H Output Enable X L H L H Inhibit H X H L H Inhibit L H Output Enable X X L L H Reset X: Dont care 2 2016-12-02