TC74VHC175FT(SPL) Toshiba

TC74VHC175F/FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC175F, TC74VHC175FT, TC74VHC175FK Quad D-Type Flip Flop with Clear TC74VHC175F The TC74VHC175 is an advanced high speed CMOS QUAD 2 D-TYPE FLIP FLOP fabricated with silicon gate C MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. These four flip-flops are controlled by a clock input (CK) and a clear input ( CLR ). The information data applied to the D inputs (D1 thru D4) are TC74VHC175FT transferred to the outputs (Q1 thru Q4 and Q t1 hru Q4 ) on the positive-going edge of the clock pulse. When the CLR input is held low, the Q outputs are at the low logic level and the Q outputs are at the high logic level, regardless of other input conditions. An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. TC74VHC175FK Features High speed: f = 210 MHz (typ.) at V = 5 V max CC Low power dissipation: I = 4 A (max) at Ta = 25C CC High noise immunity: V = V = 28% V (min) NIH NIL CC Power down protection is provided on all inputs. Balanced propagation delays: t t pLH pHL Wide operating voltage range: V = 2 to 5.5 V CC (opr) Weight Low noise: V = 0.8 V (max) OLP SOP16-P-300-1.27A : 0.18 g (typ.) Pin and function compatible with 74ALS175 TSSOP16-P-0044-0.65A : 0.06 g (typ.) VSSOP16-P-0030-0.50 : 0.02 g (typ.) Start of commercial production 1991-11 1 2014-03-01 TC74VHC175F/FT/FK Pin Assignment IEC Logic Symbol (1) CLR R 1 16 V CLR CC (9) CK C1 Q1 2 15 Q4 (2) Q1 (4) 1D D1 (3) Q1 14 Q4 3 Q1 (7) Q2 (5) D1 4 13 D4 D2 (6) Q2 (10) Q3 D2 5 12 D3 (12) D3 (11) Q3 (15) Q2 6 11 Q3 Q4 (13) D4 (14) Q4 Q2 7 10 Q3 GND 8 CK 9 (top view) Truth Table Inputs Outputs Function CLR D CK Q Q L X X L H Clear H L L H H H H L H X Q No Change Q n n X: Dont care System Diagram D1 D2 D3 D4 4 5 12 13 1 CLR R R R R D Q D Q D Q D Q CK Q CK Q CK Q CK Q 9 CK 2 3 7 6 10 11 15 14 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 2 2014-03-01