TC75S55FU(TE85L,F) Toshiba

TC75S55F/FU TOSHIBA CMOS Linear Integrated Circuit Silicon Monolithic TC75S55F, TC75S55FU Single Operational Amplifier TC75S55F The TC75S55F/TC75S55FU is a CMOS single-operation amplifier which incorporates a phase compensation circuit. It is designed for use with a low- voltage, low-current power supply this differentiates this device from conventional general-purpose bipolar op-amps. Features (SMV) Low-voltage operation : V = 0.9 to 3.5 V or 1.8 to 7 V DD TC75S55FU Low-current power supply : I (V = 3 V) = 10 A (typ.) DD DD Built-in phase-compensated op-amp, obviating the need for any external device Ultra-compact package Absolute Maximum Ratings (Ta = 25C) (USV) Weight Characteristics Symbol Rating Unit SSOP5-P-0.95 : 0.014 g (typ.) Supply voltage V , V 7 V DD SS SSOP5-P-0.65A : 0.006 g (typ.) Differential input voltage DV 7 V IN Input voltage V V V V IN DD to SS Power dissipation P 200 mW D Operating temperature T 40 to 85 C opr Storage temperature T 55 to 125 C stg Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Start of commercial production 1995-01 2019 2019-09-11 1 Toshiba Electronic Devices & Storage Corporation TC75S55F/FU Marking (top view) Pin Connection (top view) V OUT DD 5 4 5 4 S F 1 2 3 IN (+) V IN () 1 2 3 SS Electrical Characteristics DC Characteristics (V = 3.0 V, V = GND, Ta = 25C) DD SS Test Characteristics Symbol Test Condition Min Typ. Max Unit Circuit Input offset voltage V 1 R = 10 k 2 10 mV IO S Input offset current I 1 pA IO Input bias current I 1 pA I Common mode input voltage CMV 2 0.0 2.1 V IN Voltage gain (open loop) G 60 70 dB V 3 R 1 M 2.9 VOH L Maximum output voltage V V 4 R 1 M 0.1 OL L Common mode input signal CMRR 2 V = 0.0 to 2.1 V 60 70 dB IN Rejection Ratio Supply voltage rejection ratio SVRR 1 V = 1.8 to 7.0 V 60 70 dB DD Supply current I 5 10 20 A DD Source current I 6 10 20 A source Sink current I 7 100 450 A sink DC Characteristics (V = 1.8 V, V = GND, Ta = 25C) DD SS Test Characteristics Symbol Test Condition Min Typ. Max Unit Circuit Input offset voltage V 1 R = 100 k 2 10 mV IO S Input offset current I 1 pA IO Input bias current I 1 pA I Common mode input voltage CMV 2 0.0 0.9 V IN Voltage gain (open loop) G 60 70 dB V V 3 R 1 M 1.7 OH L Maximum output voltage V V 4 R 1 M 0.1 OL L Supply current I 5 8 16 A DD Source current I 6 8 16 A source Sink current I 7 100 400 A sink 2019 2019-09-11 2 Toshiba Electronic Devices & Storage Corporation