TC7WU04FK,LF Toshiba

TC7WU04FU/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7WU04FU, TC7WU04FK 3 Inverters The TC7WU04 is a high speed CMOS Inverter fabricated with silicon gate CMOS technology. TC7WU04FU It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. As the internal circuit is composed of single stage inverter, it can be applied for crystal oscillation. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features High speed: t = 6 ns (typ.) at V = 4.5 V pd CC (SM8) Low power dissipation: I = 1 A (max) at Ta = 25C CC TC7WU04FK High noise immunity: V = V = 10% V (min) NIH NIL CC Output drive capability: 10 LSTTL loads Symmetrical output impedance: I = I = 4 mA (min) OH OL Balanced propagation delays: t t pLH pHL Wide operating voltage range: V (opr) = 2 to 6 V CC Marking (US8) Weight TC7WU04FU SSOP8-P-0.65: 0.02 g (typ.) Part No. SSOP8-P-0.50A: 0.01 g (typ.) 7 W U 0 4 Lot No. TC7WU04FK Part No. W U 0 4 Start of commercial production 1991-09 1 2014-11-18 TC7WU04FU/FK Absolute Maximum Ratings (Ta = 25C) Characteristics Symbol Rating Unit Supply voltage range V 0.5 to 7 V CC DC input voltage V 0.5 to V + 0.5 V IN CC DC output voltage V 0.5 to V + 0.5 V OUT CC Input diode current I 20 mA IK Output diode current I 20 mA OK DC output current I 25 mA OUT DC V /ground current I 25 mA CC CC 300 (SM8) Power dissipation P mW D 200 (US8) Storage temperature range T 65 to 150 C stg Lead temperature (10 s) T 260 C L Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (Handling Precautions/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). Pin Configuration (top view) V 1Y 3A 2Y CC 8 7 6 5 1 2 3 4 1A 3Y 2A GND Logic Diagram (1) (7) 1A 1 1Y (3) (5) 2A 2Y (6) (2) 3A 3Y Truth Table A Y L H H L 2 2014-11-18