Not Recommended for New Designs P045F048T17AL PRM TM PRM Regulator TM 45 V input VI Chip PRM Adaptive Loop feedback Vin range 38 55 Vdc ZVS buck-boost regulator 3 V = 38 55 V High density 576 W/in 1.45 MHz switching frequency IN V = 26 55 V F 2 Small footprint 153 W/in 97% efficiency P = 170 W F Low weight 0.5 oz (15 g) 125C operation (T ) J I = 3.5 A F Product Description Absolute Maximum Ratings The VI Chip regulator is a very efficient non-isolated Parameter Values Unit Notes regulator capable of both boosting and bucking a wide +In to -In -1.0 to 85.0 Vdc range input voltage. It is specifically designed to provide PC to -In -0.3 to 6.0 Vdc a controlled Factorized Bus distribution voltage for TM PR to -In -0.3 to 9.0 Vdc powering downstream VTM Transformer fast, IL to -In -0.3 to 6.0 Vdc efficient, isolated, low noise Point-of-Load (POL) TM converters. In combination, PRMs and VTMs form a VC to -In -0.3 to 18.0 Vdc complete DC-DC converter subsystem offering all of the +Out to -Out -0.3 to 59 Vdc TM unique benefits of Vicors Factorized Power Architecture SC to -Out -0.3 to 3.0 Vdc TM (FPA) : high density and efficiency low noise VH to -Out -0.3 to 9.5 Vdc operation architectural flexibility extremely fast OS to -Out -0.3 to 9.0 Vdc transient response and elimination of bulk capacitance CD to -Out -0.3 to 9.0 Vdc at the Point-of-Load (POL). SG to -Out 100 mA In FPA systems, the POL voltage is the product of the Continuous output current 3.54 Adc Factorized Bus voltage delivered by the PRM and the Continuous output power 170 WK-facto (the fixed voltage transformation ratio) of a downstream VTM. The PRM controls the Factorized Bus 225 C MSL 5 Case temperature during reflow voltage to provide regulation at the POL. Because VTMs 245 C MSL 6 perform true voltage division and current multiplication, Operating junction temperature -40 to 125 C T-Grade the Factorized Bus voltage may be set to a value that is Storage temperature -40 to 125 C T-Grade substantially higher than the bus voltages typically found inintermediate bu systems, reducing DC-DC Converter distribution losses and enabling use of narrower distribution bus traces. A PRM-VTM chip set can provide up to 100 A or 160 W at a FPA system density of 3 3 VC VH 169 A/in or 271 W/in and because the PRM can be SC PC +Out Factorized +In 0.01 F TM SG located, orfactorized remotely from the POL, these IL OS Bus (V ) NC F L NC ROS power densities can be effectively doubled. PR PRM -AL +Out CD 10 k Module RCD TM O VTM +In +Out VC Module The PRM described in this data sheet features a unique PC 0.4 H A OutAdaptive Loo compensation feedback: a single wire V IN 10 K D In In Out alternative to traditional remote sensing and feedback Out Ro loops that enables precise control of an isolated POL voltage without the need for either a direct connection The P045F048T17AL is used with any 048 input series VTM to provide a regulated and to the load or for noise sensitive, bandwidth limiting, isolated output. isolation devices in the feedback path. vicorpower.com 800-735-6200 VI Chip Regulator P045F048T17AL Rev. 2.6 Page 1 of 14Not Recommended for New Designs VI Chip Regulator General Specifications Part Numbering P 045 F 048 T 17 AL Input Voltage Configuration Product Grade Temperatures (C) AL = Adaptive Loop Nominal Output Power Regulator F = J-lead Grade Storage Operating (T ) Designator Factorized Bus J Designator T = Through hole T -40 to125 -40 to125 (=P /10) Voltage f Overview of Adaptive Loop Compensation Adaptive Loop compensation, illustrated in Figure 1, contributes to the The VI Chips bi-directional VC port : bandwidth and speed advantage of Factorized Power. The PRM 1. Provides a wake up signal from the PRM to the VTM that monitors its output current and automatically adjusts its output voltage synchronizes the rise of the VTM output voltage to that of the PRM. to compensate for the voltage drop in the output resistance of the 2. Provides feedback from the VTM to the PRM to enable the PRM to VTM. R sets the desired value of the VTM output voltage, Vout R OS CD compensate for the voltage drop in VTM output resistance, R . O is set to a value that compensates for the output resistance of the VTM (which, ideally, is located at the point of load). For selection of R and R , refer to Table 1 below or Page 9. OS CD VC VH SC PC +Out Factorized +In 0.01 F SG TM IL OS Bus (V ) NC F L NC ROS PR PRM -AL +Out CD 10 k RCD TM Module O VTM VC +In +Out Module PC 0.4 H A Out V IN 10 K D In In Out Out Ro Figure 1 With Adaptive Loop control, the output of the VTM is regulated over the load current range with only a single interconnect between the PRM and VTM and without the need for isolation in the feedback path. (1) (2) (3) (3) Desired Load Voltage (Vdc) VTM P/N Max VTM Output Current (A) R (k) R () OS CD 1.0 V048F015T100 100 3.57 26.1 1.2 V048F015T100 100 2.94 32.4 1.5 V048F015T100 100 2.37 39.2 1.8 V048F020T080 80 2.61 35.7 2.0 V048F020T080 80 2.37 39.2 3.0 V048F030T070 70 2.37 39.2 3.3 V048F040T050 50 2.89 32.6 5.0 V048F060T040 40 2.87 33.2 8.0 V048F080T030 30 2.37 32.9 9.6 V048F096T025 25 2.37 32.9 10 V048F120T025 25 2.86 32.9 12 V048F120T025 25 2.37 39.2 15 V048F160T015 15 2.49 37.4 24 V048F240T012 12.5 2.37 39.2 28 V048F320T009 9.4 2.74 35.7 36 V048F480T006 6.3 3.16 30.1 48 V048F480T006 6.3 2.37 39.2 Note: (1) See Table 2 on page 9 for nominal Vout range and K factors. (2) See PRM output power vs. VTM output power on Page 10 (3) 1% precision resistors recommended Table 1 Configure your Chip Set using the PRM-AL vicorpower.com 800-735-6200 VI Chip Regulator P045F048T17AL Rev. 2.6 Page 2 of 14