QPI-10
QUIETPOWER
TM
AdvancedTCA Hot-Swap SiP with VI Chip EMI Filter
Description Features
>40 dB CM attenuation at 1 MHz
The QPI-10 integrates a total hot-swap function with
an EMI filter for VI Chip applications. The product
>60 dB DM attenuation at 1 MHz
TM
aligns with the AdvancedTCA PICMG3.0
80 Vdc (max input)
require-ments for hot insertion and board level
100 Vdc surge 100 msec
conducted noise limitations. The EMI filter provides
1500 V hipot hold off to shield
conducted common-mode (CM) and differential-mode
(DM) noise attenuation from 150 kHz to 30 MHz.
6 A breaker with delay plus 12 A limiter
The QPI-10 is designed for use on a 48 or 60 Vdc bus
25 mm x 25 mm x 4.5 mm SiP (System-in-Package)
(36 76 Vdc). The inrush current limit and circuit
Low profile LGA package
breaker are designed to satisfy the 200 W per board
-40 to +100C PCB temperature (See Fig. 5)
PICMG3.0 limit up to 70C PCB temperature around
the QPI-10.
Hot-swap & filter combined saves PCB space
The under and overvoltage thresholds can be trimmed
Efficiency ~99%
separately via the UVEN and OV inputs using external
Connects between ORing diodes & power
series resistors. The QPI-10 provides two Power Good
conversion input hold-up capacitance
signals, with one referenced to the input ground and
Patents pending
the other to the output ground, which can be used to
TV approval
enable other circuits along with the VI Chip converter.
Applications
Telecom & ATCA PICMG 3.0 boards using
Vicors VI Chip technology
Figure 1 Block Diagram Figure 2 Typical Attenuation
Picor Corporation www.picorpower.com QPI-10 Data Sheet Rev. 1.4 Page 1 of 8Absolute Maximum Ratings Exceeding these parameters may result in permanent damage to the product.
Pins Parameter Notes Min Typ Max Units
BUS+, SW, PWRGD1,
Input voltage Continuous -0.5 80 Vdc
PWRGD2 to BUS-
BUS+, SW, PWRGD1,
Input voltage 100 ms transient 100 Vdc
PWRGD2 to BUS-
BUS+ / BUS- to Shield BUS inputs to shield hipot +/-1500 Vdc
QPI+ to QPI- Input to output current Pulsed limit @ 25C 12 Adc
Package Power dissipation VBUS = 48 V, 6 Adc, 25C 3.0 W
Package Operating temperature PCB to QPI interface -40 100 C
Package Thermal resistance Free air 50 C/W
Package Junction temperature Tb = 100 C Pd = 3W @15C/W 145 C
(1)
Package Thermal resistance PCB layout dependent 15 C/W
Package Storage temperature -40 125 C
(2)
Package Reflow temperature 20 s exposure @ 212 C
All Pins ESD HBM +/-2 kV
Note 1: Refer to Figure 14 and Figure 15 for critical PCB layout guidelines to achieve this thermal resistance when reflowed onto the PCB.
Note 2: RoHS compliant product maximum peak temperature is 245C for 20 seconds.
Electrical Characteristics Parameter limits apply over the operating PCB temperature range unless otherwise noted
Symbol Parameter Notes Min Typ Max Units
(3)
Vb+b- BUS+ to BUS- input range Measured at 5 A UV 80 Vdc
(3)
V+oi BUS+ to QPI+ voltage drop Measured at 5 A 110 mVdc
(3)
V-oi BUS- to QPI- voltage drop Measured at 5 A -380 mVdc
CMIL Common-mode insertion loss VBUS = 48 V frequency =1 MHz 40 dB
DMIL Differential-mode insertion loss VBUS = 48 V frequency =1 MHz 60 dB
I BUS+ to BUS- Input bias current at 80 V Input current from BUS+ to BUS- 10 mA
IPG QPI+ to QPI- Load current prior to PWRGD Critical maximum DC load 25 mA
UV Undervoltage threshold - rising Controller disabled to enabled 34 V
UVHYS Undervoltage hysteresis - falling Controller enabled to disabled UV - 2 V V
OV Overvoltage threshold - rising Controller enabled to disabled 76 V
OVHYS Overvoltage hysteresis - falling Controller disabled to enabled OV - 4 V V
PWRGD1SAT Power Good low voltage IPWG = 1 mA, referenced to BUS- 0.2 0.6 mV
PWRGD2SAT Power Good low voltage IPWG = 1 mA, referenced to QPI- 0.2 0.6 mV
PWGLK Power Good high leakage VPWG = 80 V 1 A
Note 3: Refer to Figure 5 for current derating curve
Pad Description
Pin
Number Name Description
PWRGD2 PWRGD1 OV BUS+
1, 16 BUS- Negative bus potential
9 10 11 12
Negative rail controlled by hot insertion
2, 3, 15 SW BUS+
QPI+
8 13
function.
Shield connects to the converter shield
4 SHIELD
and Y capacitor common point via RY UVEN
7 14
QPI-10
5, 6 QPI- Negative input to the converter
SiP Package
7, 8 QPI+ Positive input to the converter (Bottom View)
6 15 SW
Open drain, referenced to BUS-, that
10 PWRGD1
asserts low when power is NOT good
QPI-
5 16
BUS-
Open drain, referenced to QPI-, that
9 PWRGD2
asserts low when power is NOT good
4 3 2 1
12, 13 BUS+ Positive bus potential
14 UVEN Highside of UV resistor divider
SHIELD SW BUS-
11 OV Highside of OV resistor divider
Picor Corporation www.picorpower.com QPI-10 Data Sheet Rev. 1.4 Page 2 of 8