LTE RACH Detector v3.1 PB021 February 4, 2021 LogiCORE IP Product Brief LogiCORE IP Facts Table Introduction Core Specifics The Xilinx LogiCORE IP LTE RACH Detector Versal ACAP core decodes PRACH data encoded according UltraScale+ Supported to the E-UTRA Physical channels and UltraScale (1) Device Family Zynq-7000 SoC modulation (3GPP TS 36.211 v13.0.0) 7 Series specification. Supported User AXI4-Stream Interface Interfaces AXI4-Register Interface Additional Documentation Performance and Resource Utilization web page Resources (registration required) Provided with Core A full product guide is available for this core. Design Files VHDL and Netlist Access to this material may be requested by clicking on this registration link: Example Not Provided Design www.xilinx.com/member/lte rach detector eval.html Test Bench Not Provided Constraints File Not Provided Features Simulation Encrypted VHDL Model C Model Channel detection for 3GPP TS 36.211 Supported v13.0.0 Not Applicable S/W Driver Supports Formats 0-4 (2) Tested Design Tools Supports bandwidths: 1.4, 3, 5, 10, 15, and Design Entry Vivado Design Suite 20 MHz For supported simulators, see the Simulation Xilinx Design Tools: Release Notes Guide. Supports up to 64 roots Synthesis Vivado Synthesis Supports up to 4 antennas Support Release Notes Supports multiplexing in frequency, for up and Known Master Answer Record: 54487 to 6 frequency channels Issues C model available for the core All Vivado IP Master Vivado IP Change Logs: 72775 Change Logs Fully optimized for speed and area Xilinx Support web page Fully synchronous design using either a Notes: single clock or separate core and AXI clocks 1. For a complete listing of supported devices, see the Vivado IP catalog. 2. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide. Copyright 2014-2021 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. LTE RACH Detector v3.1 1 Send Feedback PB021 February 4, 2021 www.xilinx.comProduct Brief Overview The LTE RACH detector core provides a RACH detection solution for the E-UTRA Physical channels and modulation (3GPP TS 36.211 v13.0.0) specification. The LTE RACH detector searches through the received antenna samples and correlates against one or more (up to 64) RACH preamble sequences. The preamble sequences are based on Zadoff-Chu sequences, as defined in section 5.7 of 3GPP TS 36.211 v13.0.0. At the eNode-B, the correlation results from the RACH detector are used to detect UE access attempts and compute/update UE transmission timing advance to ensure that the signals received from all UEs are time synchronized within the cyclic prefix (CP). To accommodate different cell sizes and Doppler conditions, five different RACH formats can be used. Format 0 occupies a single subframe Formats 1 and 2 occupy two subframes Format 3 occupies three subframes. Format 4 is available for TDD mode only. The LTE RACH detector can be used to receive RACH transmissions in all five formats. Within LTE, multiple system bandwidths are supported. The LTE RACH detector can process samples for 1.4, 3, 5, 10, 15, and 20 MHz systems. The RACH detector core performs a cyclic correlation for each Zadoff-Chu sequence it is configured to detect. This identifies all of the peaks resulting from each cyclic shifted copy of the root. The transmitted RACH sequence can be multiplexed across up to six frequency channels. Allocation in frequency is achieved by modulating the RACH preamble during baseband signal generation. The RACH detector core demultiplexes these channels, and performs a correlation against the Zadoff-Chu sequences for each channel. The architecture has been designed to provide efficient use of the FPGA. All processing-intensive and timing-critical operations are performed by the FPGA. The interface to the core can be attached to any bus-based system. The memory-mapped interface allows for simple integration and validation within the system. LTE RACH Detector v3.1 2 Send Feedback PB021 February 4, 2021 www.xilinx.com