57 XA Spartan-3A Automotive FPGA Family Data Sheet DS681 (v2.1) February 5, 2021 Product Specification Summary The Xilinx Automotive (XA) Spartan-3A family of FPGAs 640+ Mb/s data transfer rate per differential I/O solves the design challenges in most high-volume, LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O cost-sensitive, I/O-intensive automotive electronics with integrated differential termination resistors applications. The four-member family offers densities Enhanced Double Data Rate (DDR) support ranging from 200,000 to 1.4 million system gates, as shown DDR/DDR2 SDRAM support up to 266 Mb/s in Table 1. Fully compliant 32-/64-bit, 33 MHz PCI technology support Introduction Abundant, flexible logic resources Densities up to 25,344 logic cells, including optional shift XA devices are available in both extended-temperature register or distributed RAM support Q-Grade (40C to +125C T ) and I-Grade (40C to J +100C T ) and are qualified to the industry recognized Efficient wide multiplexers, wide logic J AEC-Q100 standard. Fast look-ahead carry logic Enhanced 18 x 18 multipliers with optional pipeline The XA Spartan-3A family builds on the success of the IEEE 1149.1/1532 JTAG programming/debug port earlier XA Spartan-3E and XA Spartan-3 FPGA families by increasing the amount of I/O per logic, significantly reducing Hierarchical SelectRAM memory architecture the cost per I/O. New features improve system performance Up to 576 Kbits of fast block RAM with byte write enables and reduce the cost of configuration. These XA Spartan-3A for processor applications family enhancements, combined with proven 90 nm process Up to 176 Kbits of efficient distributed RAM technology, deliver more functionality and bandwidth per Up to eight Digital Clock Managers (DCMs) dollar than ever before, setting the new standard in the Clock skew elimination (delay locked loop) programmable logic industry. Frequency synthesis, multiplication, division Because of their exceptionally low cost, XA Spartan-3A High-resolution phase shifting FPGAs are ideally suited to a wide range of automotive Wide frequency range (5 MHz to over 320 MHz) electronics applications, including infotainment, driver Eight low-skew global clock networks, eight additional information, and driver assistance modules. clocks per half device, plus abundant low-skew routing The XA Spartan-3A family is a superior alternative to mask Configuration interface to industry-standard PROMs programmed ASICs. FPGAs avoid the high initial mask set Low-cost, space-saving SPI serial Flash PROM costs and lengthy development cycles, while also permitting x8 or x8/x16 parallel NOR Flash PROM design upgrades in the field with no hardware replacement Unique Device DNA identifier for design authentication necessary because of its inherent programmability, an Complete Xilinx ISE and WebPACK software impossibility with conventional ASICs and ASSPs with their support plus Spartan-3A Starter Kit inflexible architecture. MicroBlaze and PicoBlaze embedded processor cores Features BGA packaging, Pb-free ONLY Very low cost, high-performance logic solution for Common footprints support easy density migration high-volume, cost-conscious applications Refer to the Spartan-3A FPGA Family Data Sheet (DS529) Dual-range V supply simplifies 3.3V-only design CCAUX for a full product description, AC and DC specifications, and Suspend, Hibernate modes reduce system power package pinout descriptions. Any values shown specifically Multi-voltage, multi-standard SelectIO interface pins in this XA Spartan-3A Automotive FPGA Family data sheet Up to 375 I/O pins or 165 differential signal pairs override those shown in DS529. LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O For information regarding reliability qualification, refer to 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling Selectable output drive, up to 24 mA per pin RPT103 (Xilinx Spartan-3A Family Automotive Qualification QUIETIO standard reduces I/O switching noise Report) and RPT070 (Spartan-3A Commercial Qualification Full 3.3V 10% compatibility and hot swap compliance Report). Copyright 20082021 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners. DS681 (v2.1) February 5, 2021 www.xilinx.com Send Feedback Product Specification 1XA Spartan-3A Automotive FPGA Family Data Sheet Key Feature Differences from Commercial XC Devices AEC-Q100 device qualification and full production part approval process (PPAP) documentation support available in both extended temperature I- and Q-Grades Guaranteed to meet full electrical specification over the T = 40C to +125C temperature range (Q-Grade) J XA Spartan-3A devices are available in the -4 speed grade only PCI-66 is not supported in the XA Spartan-3A FPGA product line Platform Flash is not supported within the XA family XA Spartan-3A devices are available in Pb-Free packaging only. MultiBoot is not supported in XA versions of this product. The XA Spartan-3A device must be power cycled prior to reconfiguration. Table 1: Summary of XA Spartan-3A FPGA Attributes) CLB Array Equivalent Block Maximum (One CLB = Four Slices) System Distributed Dedicated Maximum Device Logic RAM DCMs Differential (1) Gates RAM bits Multipliers User I/O Total Total (1) Cells bits I/O Pairs Rows Columns CLBs Slices XA3S200A 200K 4,032 32 16 448 1,792 28K 288K 16 4 195 90 XA3S400A 400K 8,064 40 24 896 3,584 56K 360K 20 4 311 142 XA3S700A 700K 13,248 48 32 1,472 5,888 92K 360K 20 8 372 165 XA3S1400A 1400K 25,344 72 40 2,816 11,264 176K 576K 32 8 375 165 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. Architectural Overview The XA Spartan-3A family architecture consists of five fundamental programmable functional elements: Configurable Logic Blocks (CLBs) contain flexible Look-Up Tables (LUTs) that implement logic plus storage elements used as flip-flops or latches. CLBs perform a wide variety of logical functions as well as store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. IOBs support bidirectional data flow plus 3-state operation. Supports a variety of signal standards, including several high-performance differential standards. Double Data-Rate (DDR) registers are included. Block RAM provides data storage in the form of 18-Kb dual-port blocks. Multiplier Blocks accept two 18-bit binary numbers as inputs and calculate the product. Digital Clock Manager (DCM) Blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase-shifting clock signals.These elements are organized as shown in Figure 1. A dual ring of staggered IOBs surrounds a regular array of CLBs. Each device has two columns of block RAM. Each RAM column consists of several 18-Kb RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XA3S700A and XA3S1400A add two DCMs in the middle of the two columns of block RAM and multipliers. The XA Spartan-3A family features a rich network of routing that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. DS681 (v2.1) February 5, 2021 www.xilinx.com Send Feedback Product Specification 2