10 XA Artix-7 FPGAs Data Sheet: Overview DS197 (v1.3) November 15, 2017 Product Specification General Description Xilinx XA Artix-7 (Automotive) FPGAs are optimized for the lowest cost and power with small form-factor packaging for high-volume automotive applications. Designers can leverage more logic per watt compared to the Spartan-6 family. Built on a state-of-the-art high-performance/low-power (HPL) 28 nm high-k metal gate (HKMG) process technology, XA Artix-7 FPGAs redefine low-cost alternatives with more logic per watt. Unparalleled increase in system performance with 52 Gb/s I/O bandwidth, 100,000 logic cell capacity, 264 GMAC/s DSP, and flexible built-in DDR3 memory interfaces enable a new class of high-throughput, low-cost automotive applications. XA Artix-7 FPGAs also offer many high-end features, such as integrated advanced Analog Mixed Signal (AMS) technology. Analog becomes the next level of integration through the seamless implementation of independent dual 12-bit, 1 MSPS, 17-channel analog-to-digital converters. Most importantly, XA Artix-7 FPGAs proudly meet the high standards of the automotive grade with a maximum temperature of 125C. Summary of XA Artix-7 FPGA Features Automotive Temperatures: A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and I-Grade: Tj= 40C to +100C supply sensors. Q-Grade: Tj= 40C to +125C Single-ended and differential I/O standards with speeds of up to Automotive Standards: 1.25 Gb/s ISO-TS16949 compliant 240 DSP48E1 slices with up to 264 GMACs of signal processing AEC-Q100 qualification Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high Production Part Approval Process (PPAP) documentation precision and low jitter Beyond AEC-Q100 qualification is available upon request Integrated block for PCI Express (PCIe), for up to x4 Gen2 Advanced high-performance FPGA logic based on real 6-input look- Endpoint up table (LUT) technology configurable as distributed memory Wide variety of configuration options, including support for 36 Kb dual-port block RAM with built-in FIFO logic for on-chip data commodity memories, 256-bit AES encryption with HMAC/SHA-256 buffering authentication, and built-in SEU detection and correction Sub-watt performance in 100,000 logic cells Low-cost wire-bond packaging, offering easy migration between High-performance SelectIO technology with support for DDR3 family members in the same package, all packages available Pb-free interfaces up to 800 Mb/s Designed for high performance and lowest power with 28 nm, High-speed serial connectivity with built-in serial transceivers from HKMG, HPL process, 1.0V core voltage process technology 500 Mb/s to maximum rates of 6.25 Gb/s, enabling 50 Gb/s peak Strong automotive-specific third-party ecosystem with IP, bandwidth (full duplex) development boards, and design services XA Artix-7 FPGA Summary Tables Table 1: XA Artix-7 FPGA Device-Feature Table Configurable Logic (3) Block RAM Blocks Blocks (CLBs) Logic DSP48E1 XADC Total I/O Max User (4) (5) Device CMTs PCIe GTPs (2) (6) (7) Cells Max Slices Blocks Banks I/O Max (1) Slices Distributed 18 Kb 36 Kb (Kb) RAM (Kb) XA7A12T12,8002,000 171 40 40 20720 31213 150 XA7A15T16,6402,600 200 45 50 25900 51415 210 XA7A25T23,3603,650 313 80 90 451,620 31413 150 XA7A35T33,2805,200 400 90 100501,800 51415 210 XA7A50T52,1608,150 600 120 150752,700 51415 210 XA7A75T75,52011,800 892 180 2101053,780 61416 285 XA7A100T101,44015,850 1,188 240 2701354,860 61416 285 Notes: 1. Each 7 series FPGA slice contains four LUTs and eight flip-flops only some slices can use their LUTs as distributed RAM or SRLs. 2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator. 3. Block RAMs are fundamentally 36 Kb in size each block can also be used as two independent 18 Kb blocks. 4. Each CMT contains one MMCM and one PLL. 5. XA Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2. 6. Does not include configuration Bank 0. 7. This number does not include GTP transceivers. Copyright 20142017 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, UltraScale, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS197 (v1.3) November 15, 2017 www.xilinx.com Product Specification 1XA Artix-7 FPGAs Data Sheet: Overview Table 2: XA Artix-7 FPGA Device-Package Combinations and Maximum I/Os (1) Package CPG236 CPG238 CSG324 CSG325 FGG484 Size (mm) 10 x 10 10 x 10 15 x 15 15 x 15 23 x 23 Ball Pitch (mm) 0.5 0.5 0.8 0.8 1.0 I/O I/O I/O I/O I/O Device GTP GTP GTP GTP GTP (2) (2) (2) (2) (2) HR HR HR HR HR XA7A12T 2 112 2 150 XA7A15T 2 106 02104150 XA7A25T 2 112 4 150 XA7A35T 2 106 02104150 XA7A50T 2 106 02104150 XA7A75T 0210 4285 XA7A100T 0210 4285 Notes: 1. All packages listed are Pb-free. 2. HR = High Range I/O with support for I/O voltage from 1.2V to 3.3V. CLBs, Slices, and LUTs Some key features of the CLB architecture include: Real 6-input look-up tables (LUTs) Memory capability within the LUT Register and shift register functionality The LUTs in 7 series FPGAs can be configured as either one 6-input LUT (64-bit ROMs) with one output, or as two 5-input LUTs (32-bit ROMs) with separate outputs but common addresses or logic inputs. Each LUT output can optionally be registered in a flip-flop. Four such LUTs and their eight flip-flops as well as multiplexers and arithmetic carry logic form a slice, and two slices form a configurable logic block (CLB). Four of the eight flip-flops per slice (one per LUT) can optionally be configured as latches. Between 2550% of all slices can also use their LUTs as distributed 64-bit RAM or as 32-bit shift registers (SRL32) or as two SRL16s. Modern synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features. Clock Management Some of the key highlights of the clock management architecture include: High-speed buffers and routing for low-skew clock distribution Frequency synthesis and phase shifting Low-jitter clock generation and jitter filtering Each XA Artix-7 FPGA has three to six clock management tiles (CMTs), each consisting of one mixed-mode clock manager (MMCM) and one phase-locked loop (PLL). DS197 (v1.3) November 15, 2017 www.xilinx.com Product Specification 2