0 R XC2C32A CoolRunner-II CPLD 00 DS310 (v2.1) November 6, 2008 Product Specification Features Description Optimized for 1.8V systems The CoolRunner-II 32-macrocell device is designed for both high performance and low power applications. This - As fast as 3.8 ns pin-to-pin logic delays lends power savings to high-end communication equipment - As low as 12 A quiescent current and high speed to battery operated devices. Due to the low Industrys best 0.18 micron CMOS CPLD power stand-by and dynamic operation, overall system reli- - Optimized architecture for effective logic synthesis ability is improved. - Multi-voltage I/O operation: 1.5V through 3.3V This device consists of two Function Blocks interconnected Available in multiple package options by a low power Advanced Interconnect Matrix (AIM). The - 32-land QFN with 21 user I/Os AIM feeds 40 true and complement inputs to each Function - 44-pin VQFP with 33 user I/Os Block. The Function Blocks consist of a 40 by 56 P-term - 56-ball CP BGA with 33 user I/Os PLA and 16 macrocells which contain numerous configura- - Pb-free available for all packages tion bits that allow for combinational or registered modes of Advanced system features operation. - Fastest in system programming Additionally, these registers can be globally reset or preset 1.8V ISP using IEEE 1532 (JTAG) interface and configured as a D or T flip-flop or as a D latch. There - IEEE1149.1 JTAG Boundary Scan Test are also multiple clock signals, both global and local product - Optional Schmitt-trigger input (per pin) term types, configured on a per macrocell basis. Output pin - Two separate I/O banks configurations include slew rate limit, bus hold, pull-up, - RealDigital 100% CMOS product term generation open drain, and programmable grounds. A Schmitt trigger - Flexible clocking modes input is available on a per input pin basis. In addition to stor- - Optional DualEDGE triggered registers ing macrocell output states, the macrocell registers can be - Global signal options with macrocell control configured asdirect inpu registers to store signals directly Multiple global clocks with phase selection per from input pins. macrocell Clocking is available on a global or Function Block basis. Multiple global output enables Global set/reset Three global clocks are available for all Function Blocks as a - Efficient control term clocks, output enables and synchronous clock source. Macrocell registers can be indi- set/resets for each macrocell and shared across vidually configured to power up to the zero or one state. A function blocks global set/reset control line is also available to asynchro- - Advanced design security nously set or reset selected registers during operation. - Open-drain output option for Wired-OR and LED Additional local clock, synchronous clock-enable, asynchro- drive nous set/reset, and output enable signals can be formed - Optional configurable grounds on unused I/Os using product terms on a per-macrocell or per-Function Block basis. - Optional bus-hold, 3-state, or weak pullup on selected I/O pins The CoolRunner-II 32-macrocell CPLD is I/O compatible - Mixed I/O voltages compatible with 1.5V, 1.8V, with standard LVTTL and LVCMOS18, LVCMOS25, and 2.5V, and 3.3V logic levels LVCMOS33 (see Table 1). This device is also 1.5V I/O com- - PLA architecture patible with the use of Schmitt-trigger inputs. Superior pinout retention Another feature that eases voltage translation is I/O bank- 100% product term routability across function ing. Two I/O banks are available on the CoolRunner-II 32A block macrocell device that permit easy interfacing to 3.3V, 2.5V, - Hot pluggable 1.8V, and 1.5V devices. Refer to the CoolRunner-II family data sheet for the archi- tecture description. 20042008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at R XC2C32A CoolRunner-II CPLD LVCMOS standard is used in 3.3V, 2.5V, and 1.8V applica- RealDigital Design Technology tions. CoolRunner-II CPLDs are also 1.5V I/O compatible Xilinx CoolRunner-II CPLDs are fabricated on a with the use of Schmitt-trigger inputs. 0.18 micron process technology which is derived from lead- ing edge FPGA product development. CoolRunner-II Table 1: I/O Standards for XC2C32A CPLDs employ RealDigital, a design technique that makes Board use of CMOS technology in both the fabrication and design IOSTANDARD Output Input Input Termination methodology. RealDigital design technology employs a cas- Attribute V V V Voltage V CCIO CCIO REF T cade of CMOS gates to implement sum of products instead LVTTL 3.3 3.3 N/A N/A of traditional sense amplifier methodology. Due to this tech- nology, Xilinx CoolRunner-II CPLDs achieve both high per- LVCMOS33 3.3 3.3 N/A N/A formance and low power operation. LVCMOS25 2.5 2.5 N/A N/A LVCMOS18 1.8 1.8 N/A N/A Supported I/O Standards (1) LVCMOS15 1.5 1.5 N/A N/A The CoolRunner-II CPLD 32 macrocell features both 1. LVCMOS15 requires Schmitt-trigger inputs. LVCMOS and LVTTL I/O implementations. See Table 1 for I/O standard voltages. The LVTTL I/O standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The 20 15 10 5 0 0 50 100 150 200 250 300 Frequency (MHz) DS091 01 030105 Figure 1: I vs. Frequency CC (1) Table 2: I vs. Frequency (LVCMOS 1.8V T = 25C) CC A Frequency (MHz) 0 25 50 75 100 150 175 200 225 250 300 Typical I (mA) 0.016 0.87 1.75 2.61 3.44 5.16 5.99 6.81 7.63 8.36 9.93 CC Notes: 1. 16-bit up/down, resettable binary counter (one counter per function block). 2 www.xilinx.com DS310 (v2.1) November 6, 2008 Product Specification I (mA) CC