0 R CoolRunner-II CPLD Family 00 DS090 (v3.1) September 11, 2008 Product Specification - SSTL2 1,SSTL3 1, and HSTL 1 on 128 Features macrocell and denser devices Optimized for 1.8V systems - Hot pluggable - Industrys fastest low power CPLD PLA architecture - Densities from 32 to 512 macrocells - Superior pinout retention Industrys best 0.18 micron CMOS CPLD - 100% product term routability across function block - Optimized architecture for effective logic synthesis Wide package availability including fine pitch: - Multi-voltage I/O operation 1.5V to 3.3V - Chip Scale Package (CSP) BGA, Fine Line BGA, Advanced system features TQFP, PQFP, VQFP, and QFN packages - Fastest in system programming - Pb-free available for all packages 1.8V ISP using IEEE 1532 (JTAG) interface Design entry/verification using Xilinx and industry - On-The-Fly Reconfiguration (OTF) standard CAE tools - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt trigger input (per pin) Free software support for all densities using Xilinx - Multiple I/O banks on all devices WebPACK tool - Unsurpassed low power management Industry leading nonvolatile 0.18 micron CMOS DataGATE external signal control process - Flexible clocking modes - Guaranteed 1,000 program/erase cycles Optional DualEDGE triggered registers - Guaranteed 20 year data retention Clock divider ( 2,4,6,8,10,12,14,16) CoolCLOCK Family Overview - Global signal options with macrocell control Xilinx CoolRunner-II CPLDs deliver the high speed and Multiple global clocks with phase selection per ease of use associated with the XC9500/XL/XV CPLD fam- macrocell ily with the extremely low power versatility of the XPLA3 Multiple global output enables family in a single CPLD. This means that the exact same Global set/reset parts can be used for high-speed data communications/ - Abundant product term clocks, output enables and computing systems and leading edge portable products, set/resets with the added benefit of In System Programming. Low - Efficient control term clocks, output enables and power consumption and high-speed operation are com- set/resets for each macrocell and shared across bined into a single family that is easy to use and cost effec- function blocks tive. Clocking techniques and other power saving features - Advanced design security extend the users power budget. The design features are - Open-drain output option for Wired-OR and LED supported starting with Xilinx ISE 4.1i WebPACK tool. drive Additional details can be found in Further Reading, - Optional bus-hold, 3-state or weak pullup on select page 14. I/O pins Table 1 shows the macrocell capacity and key timing - Optional configurable grounds on unused I/Os parameters for the CoolRunner-II CPLD family. - Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts Table 1: CoolRunner-II CPLD Family Parameters XC2C32A XC2C64A XC2C128 XC2C256 XC2C384 XC2C512 Macrocells 32 64 128 256 384 512 Max I/O 33 64 100 184 240 270 T (ns) 3.8 4.6 5.7 5.7 7.1 7.1 PD T (ns) 1.9 2.0 2.4 2.4 2.9 2.6 SU T (ns) 3.7 3.9 4.2 4.5 5.8 5.8 CO F (MHz) 323 263 244 256 217 179 SYSTEM1 20022008 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at R CoolRunner-II CPLD Family Table 2: CoolRunner-II CPLD DC Characteristics XC2C32A XC2C64A XC2C128 XC2C256 XC2C384 XC2C512 I (A), 0 MHz, 25C (typical) 16 17 19 21 23 25 CC I (mA), 50 MHz, 70C (max) 2.5 5 10 27 45 55 CC 1. I is dynamic current. CC Table 2 shows key DC characteristics for the CoolRunner-II in CoolRunner-II CPLDs generates minimal heat, allowing family. the use of tiny packages during high-speed operation. Table 3 shows the CoolRunner-II CPLD package offering With the exception of the Pb-free QF packages, there are at with corresponding I/O count. All packages are surface least two densities present in each package with three in the mount, with over half of them being ball-grid technologies. VQ100 (100-pin 1.0mm QFP), TQ144 (144-pin 1.4mm The ultra tiny packages permit maximum functional capacity QFP), and FT256 (256-ball 1.0mm spacing FLBGA). The in the smallest possible area. The CMOS technology used FT256 is particularly important for slim dimensioned porta- ble products with mid- to high-density logic requirements. Table 3: CoolRunner-II CPLD Family Packages and I/O Count XC2C32A XC2C64A XC2C128 XC2C256 XC2C384 XC2C512 (1) QFG32 21 - - - - - VQ44 33 33 - - - - (1) VQG44 33 33 - - - - (1) QFG48 -37 - - - - CP56 33 45 - - - - (1) CPG56 33 45 - - - - VQ100 - 64 80 80 - - (1) VQG100 -64 80 80 - - CP132 - - 100 106 - - (1) CPG132 - - 100 106 - - TQ144 - - 100 118 118 - (1) TQG144 - - 100 118 118 - PQ208 - - - 173 173 173 (1) PQG208 - - - 173 173 173 FT256 - - - 184 212 212 (1) FTG256 - - - 184 212 212 FG324 - - - - 240 270 (1) FGG324 - - - - 240 270 Notes: 1. The letter as the third character indicates a Pb-free package. Table 4 details the distribution of advanced features across that four I/O banks are needed on 32 and 64 macrocell the CoolRunner-II CPLD family. The family has uniform parts, but very likely they are for 384 and 512 macrocell basic features with advanced features included in densities parts. The I/O banks are groupings of I/O pins using any where they are most useful. For example, it is very unlikely one of a subset of compatible voltage standards that share 2 www.xilinx.com DS090 (v3.1) September 11, 2008 Product Specification