Product Obsolete or Under Obsolescence 0 XC3000 Series R Field Programmable Gate Arrays (XC3000A/L, XC3100A/L) 07* November 9, 1998 (Version 3.1) Product Description Complete Development System Features - Schematic capture, automatic place and route Complete line of four related Field Programmable Gate - Logic and timing simulation Array product families - Interactive design editor for design optimization - XC3000A, XC3000L, XC3100A, XC3100L - Timing calculator Ideal for a wide range of custom VLSI design tasks - Interfaces to popular design environments like - Replaces TTL, MSI, and other PLD logic Viewlogic, Cadence, Mentor Graphics, and others - Integrates complete sub-systems into a single package Additional XC3100A Features - Avoids the NRE, time delay, and risk of conventional Ultra-high-speed FPGA family with six members masked gate arrays - 50-85 MHz system clock rates High-performance CMOS static memory technology - 190 to 370 MHz guaranteed flip-flop toggle rates - Guaranteed toggle rates of 70 to 370 MHz, logic - 1.55 to 4.1 ns logic delays delays from 7 to 1.5 ns High-end additional family member in the 22 X 22 CLB - System clock speeds over 85 MHz array-size XC3195A device - Low quiescent and active power consumption 8 mA output sink current and 8 mA source current Flexible FPGA architecture Maximum power-down and quiescent current is 5 mA - Compatible arrays ranging from 1,000 to 7,500 gate 100% architecture and pin-out compatible with other complexity XC3000 families - Extensive register, combinatorial, and I/O 7 Software and bitstream compatible with the XC3000, capabilities XC3000A, and XC3000L families - High fan-out signal distribution, low-skew clock nets XC3100A combines the features of the XC3000A and - Internal 3-state bus capabilities XC3100 families: - TTL or CMOS input thresholds - On-chip crystal oscillator amplifier Additional interconnect resources for TBUFs and CE Unlimited reprogrammability inputs - Easy design iteration Error checking of the configuration bitstream - In-system logic changes Soft startup holds all outputs slew-rate limited during Extensive packaging options initial power-up - Over 20 different packages More advanced CMOS process - Plastic and ceramic surface-mount and pin-grid- array packages Low-Voltage Versions Available - Thin and Very Thin Quad Flat Pack (TQFP and Low-voltage devices function at 3.0 - 3.6 V VQFP) options XC3000L - Low-voltage versions of XC3000A devices Ready for volume production XC3100L - Low-voltage versions of XC3100A devices - Standard, off-the-shelf product availability - 100% factory pre-tested devices - Excellent reliability record Max Logic Typical Gate User I/Os Horizontal Configuration Device CLBs Array Flip-Flops Gates Range Max Longlines Data Bits XC3020A, 3020L, 3120A 1,500 1,000 - 1,500 64 8 x 8 64 256 16 14,779 XC3030A, 3030L, 3130A 2,000 1,500 - 2,000 100 10 x 10 80 360 20 22,176 XC3042A, 3042L, 3142A, 3142L 3,000 2,000 - 3,000 144 12 x 12 96 480 24 30,784 XC3064A, 3064L, 3164A 4,500 3,500 - 4,500 224 16 x 14 120 688 32 46,064 XC3090A, 3090L, 3190A, 3190L 6,000 5,000 - 6,000 320 16 x 20 144 928 40 64,160 XC3195A 7,500 6,500 - 7,500 484 22 x 22 176 1,320 44 94,984 November 9, 1998 (Version 3.1) 7-3Product Obsolete or Under Obsolescence R XC3000 Series Field Programmable Gate Arrays Here is a simple overview of those XC3000 products cur- Introduction rently emphasized: XC3000-Series Field Programmable Gate Arrays (FPGAs) XC3000A Family The XC3000A is an enhanced provide a group of high-performance, high-density, digital version of the basic XC3000 family, featuring additional integrated circuits. Their regular, extendable, flexible, interconnect resources and other user-friendly user-programmable array architecture is composed of a enhancements. configuration program store plus three types of config- XC3000L Family The XC3000L is identical in urable elements: a perimeter of I/O Blocks (IOBs), a core architecture and features to the XC3000A family, but array of Configurable Logic Bocks (CLBs) and resources operates at a nominal supply voltage of 3.3 V. The for interconnection. The general structure of an FPGA is XC3000L is the right solution for battery-operated and shown in Figure2. The development system provides low-power applications. schematic capture and auto place-and-route for design XC3100A Family The XC3100A is a entry. Logic and timing simulation, and in-circuit emulation performance-optimized relative of the XC3000A family. are available as design verification alternatives. The design While both families are bitstream and footprint editor is used for interactive design optimization, and to compatible, the XC3100A family extends toggle rates to compile the data pattern that represents the configuration 370 MHz and in-system performance to over 80 MHz. program. The XC3100A family also offers one additional array The FPGA user logic functions and interconnections are size, the XC3195A. determined by the configuration program data stored in XC3100L Family The XC3100L is identical in internal static memory cells. The program can be loaded in architectures and features to the XC3100A family, but any of several modes to accommodate various system operates at a nominal supply voltage of 3.3V. requirements. The program data resides externally in an Figure 1 illustrates the relationships between the families. EEPROM, EPROM or ROM on the application circuit Compared to the original XC3000 family, XC3000A offers board, or on a floppy disk or hard disk. On-chip initialization additional functionality and increased speed. The XC3000L logic provides for optional automatic loading of program family offers the same additional functionality, but reduced data at power-up. The companion XC17XX Serial Configu- speed due to its lower supply voltage of 3.3 V. The ration PROMs provide a very simple serial configuration XC3100A family offers substantially higher speed and program storage in a one-time programmable package. higher density with the XC3195A. The XC3000 Field Programmable Gate Array families pro- vide a variety of logic capacities, package styles, tempera- New XC3000 Series Compared to Original ture ranges and speed grades. XC3000 Family For readers already familiar with the original XC3000 family XC3000 Series Overview of FPGAs, the major new features in the XC3000A, There are now four distinct family groupings within the XC3000L, XC3100A, and XC3100L families are listed in XC3000 Series of FPGA devices: this section. XC3000A Family All of these new families are upward-compatible extensions XC3000L Family of the original XC3000 FPGA architecture. Any bitstream XC3100A Family used to configure an XC3000 device will configure the cor- XC3100L Family responding XC3000A, XC3000L, XC3100A, or XC3100L All four families share a common architecture, develop- device exactly the same way. ment software, design and programming methodology, and The XC3100A and XC3100L FPGA architectures are also common package pin-outs. An extensive Product upward-compatible extensions of the XC3000A and Description covers these common aspects. XC3000L architectures. Any bitstream used to configure an Detailed parametric information for the XC3000A, XC3000A or XC3000L device will configure the corre- XC3000L, XC3100A, and XC3100L product families is then sponding XC3100A or XC3100L device exactly the same provided. (The XC3000 and XC3100 families are not rec- way. ommended for new designs.) 7-4 November 9, 1998 (Version 3.1)