XC3S1200E-5FGG400C Xilinx

1 Spartan-3E FPGA Family Data Sheet DS312 December 14, 2018 Product Specification Module 1: Module 3: Introduction and Ordering Information DC and Switching Characteristics DS312 (v4.2) December 14, 2018 DS312 (v4.2) December 14, 2018 Introduction DC Electrical Characteristics Features Absolute Maximum Ratings Architectural Overview Supply Voltage Specifications Package Marking Recommended Operating Conditions Ordering Information DC Characteristics Switching Characteristics Module 2: I/O Timing Functional Description SLICE Timing DS312 (v4.2) December 14, 2018 DCM Timing Input/Output Blocks (IOBs) Block RAM Timing Overview Multiplier Timing SelectIO Signal Standards Configuration and JTAG Timing Configurable Logic Block (CLB) Block RAM Module 4: Pinout Descriptions Dedicated Multipliers DS312 (v4.2) December 14, 2018 Digital Clock Manager (DCM) Clock Network Pin Descriptions Configuration Package Overview Powering Spartan-3E FPGAs Pinout Tables Production Stepping Footprint Diagrams Copyright 20052018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS312 December 14, 2018 www.xilinx.com Send Feedback Product Specification 18 Spartan-3E FPGA Family: Introduction and Ordering Information DS312 (v4.2) December 14, 2018 Product Specification Introduction LVCMOS, LVTTL, HSTL, and SSTL single-ended signal The Spartan-3E family of Field-Programmable Gate standards Arrays (FPGAs) is specifically designed to meet the needs 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling of high volume, cost-sensitive consumer electronic 622+ Mb/s data transfer rate per I/O applications. The five-member family offers densities True LVDS, RSDS, mini-LVDS, differential HSTL/SSTL ranging from 100,000 to 1.6 million system gates, as shown differential I/O in Table 1. Enhanced Double Data Rate (DDR) support DDR SDRAM support up to 333 Mb/s The Spartan-3E family builds on the success of the earlier Abundant, flexible logic resources Spartan-3 family by increasing the amount of logic per I/O, Densities up to 33,192 logic cells, including optional shift significantly reducing the cost per logic cell. New features register or distributed RAM support improve system performance and reduce the cost of Efficient wide multiplexers, wide logic configuration. These Spartan-3E FPGA enhancements, Fast look-ahead carry logic combined with advanced 90 nm process technology, deliver Enhanced 18 x 18 multipliers with optional pipeline more functionality and bandwidth per dollar than was IEEE 1149.1/1532 JTAG programming/debug port previously possible, setting new standards in the Hierarchical SelectRAM memory architecture programmable logic industry. Up to 648 Kbits of fast block RAM Because of their exceptionally low cost, Spartan-3E FPGAs Up to 231 Kbits of efficient distributed RAM are ideally suited to a wide range of consumer electronics Up to eight Digital Clock Managers (DCMs) applications, including broadband access, home Clock skew elimination (delay locked loop) networking, display/projection, and digital television Frequency synthesis, multiplication, division equipment. High-resolution phase shifting Wide frequency range (5 MHz to over 300 MHz) The Spartan-3E family is a superior alternative to mask Eight global clocks plus eight additional clocks per each half programmed ASICs. FPGAs avoid the high initial cost, the of device, plus abundant low-skew routing lengthy development cycles, and the inherent inflexibility of Configuration interface to industry-standard PROMs conventional ASICs. Also, FPGA programmability permits Low-cost, space-saving SPI serial Flash PROM design upgrades in the field with no hardware replacement x8 or x8/x16 parallel NOR Flash PROM necessary, an impossibility with ASICs. Low-cost Xilinx Platform Flash with JTAG Complete Xilinx ISE and WebPACK software MicroBlaze and PicoBlaze embedded processor cores Features Fully compliant 32-/64-bit 33 MHz PCI support (66 MHz in some devices) Very low cost, high-performance logic solution for high-volume, consumer-oriented applications Low-cost QFP and BGA packaging options Common footprints support easy density migration Proven advanced 90-nanometer process technology Pb-free packaging options Multi-voltage, multi-standard SelectIO interface pins Up to 376 I/O pins or 156 differential signal pairs XA Automotive version available Table 1: Summary of Spartan-3E FPGA Attributes CLB Array Block Maximum (One CLB = Four Slices) System Equivalent Distributed Dedicated Maximum Device RAM DCMs Differential (1) Gates Logic Cells RAM bits Multipliers User I/O Total Total (1) bits I/O Pairs Rows Columns CLBs Slices XC3S100E 100K 2,160 22 16 240 960 15K 72K 4 2 108 40 XC3S250E 250K 5,508 34 26 612 2,448 38K 216K 12 4 172 68 XC3S500E 500K 10,476 46 34 1,164 4,656 73K 360K 20 4 232 92 XC3S1200E 1200K 19,512 60 46 2,168 8,672 136K 504K 28 8 304 124 XC3S1600E 1600K 33,192 76 58 3,688 14,752 231K 648K 36 8 376 156 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. Copyright 20052018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, Artix, Kintex, Zynq, Vivado, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI and PCI-X are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS312 (v4.2) December 14, 2018 www.xilinx.com Send Feedback Product Specification 2