XC3S400A-4FGG400I Xilinx

0 Spartan-3A FPGA Family: Data Sheet 00 DS529 December 18, 2018 Product Specification Module 1: Module 3: Introduction and Ordering Information DC and Switching Characteristics DS529 (v2.1) December 18, 2018 DS529 (v2.1) December 18, 2018 Introduction DC Electrical Characteristics Absolute Maximum Ratings Features Supply Voltage Specifications Architectural and Configuration Overview Recommended Operating Conditions General I/O Capabilities Switching Characteristics Production Status I/O Timing Supported Packages and Package Marking Configurable Logic Block (CLB) Timing Ordering Information Multiplier Timing Block RAM Timing Module 2: Digital Clock Manager (DCM) Timing Spartan-3A FPGA Family: Functional Suspend Mode Timing Description Device DNA Timing Configuration and JTAG Timing DS529 (v2.1) December 18, 2018 The functionality of the Spartan-3A FPGA family is Module 4: described in the following documents. Pinout Descriptions UG331: Spartan-3 Generation FPGA User Guide DS529 (v2.1) December 18, 2018 Clocking Resources Pin Descriptions Digital Clock Managers (DCMs) Package Overview Block RAM Pinout Tables Configurable Logic Blocks (CLBs) - Distributed RAM Footprint Diagrams - SRL16 Shift Registers - Carry and Arithmetic Logic For more information on the Spartan-3A FPGA family, go to I/O Resources Embedded Multiplier Blocks www.xilinx.com/spartan3a Programmable Interconnect ISE Design Tools and IP Cores Embedded Processing and Control Solutions Spartan-3A FPGA Status Pin Types and Package Overview XC3S50A Production Package Drawings Powering FPGAs XC3S200A Production Power Management UG332: Spartan-3 Generation Configuration User Guide XC3S400A Production Configuration Overview Configuration Pins and Behavior XC3S700A Production Bitstream Sizes XC3S1400A Production Detailed Descriptions by Mode - Master Serial Mode using Platform Flash PROM - Master SPI Mode using Commodity Serial Flash - Master BPI Mode using Commodity Parallel Flash - Slave Parallel (SelectMAP) using a Processor - Slave Serial using a Processor -JTAG Mode ISE iMPACT Programming Examples MultiBoot Reconfiguration Design Authentication using Device DNA UG334: Spartan-3A/3AN FPGA Starter Kit User Guide Copyright 20062018 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI is a registered trademark of the PCI-SIG. All other trademarks are the property of their respective owners. DS529 December 18, 2018 www.xilinx.com 1 Product SpecificationSpartan-3A FPGA Family: Data Sheet 2 www.xilinx.com DS529 December 18, 2018 Product Specification