Product Obsolete or Under Obsolescence 0 R XC4000E and XC4000X Series Field Programmable Gate Arrays 00* May 14, 1999 (Version 1.6) Product Specification XC4000E and XC4000X Series Low-Voltage Versions Available Features Low-Voltage Devices Function at 3.0 - 3.6 Volts XC4000XL: High Performance Low-Voltage Versions of Note: Information in this data sheet covers the XC4000E, XC4000EX devices XC4000EX, and XC4000XL families. A separate data sheet covers the XC4000XLA and XC4000XV families. Electrical Additional XC4000X Series Features Specications and package/pin information are covered in separate sections for each family to make the information High Performance 3.3 V XC4000XL easier to access, review, and print. For access to these sec- High Capacity Over 180,000 Usable Gates tions, see the Xilinx web site at 5 V tolerant I/Os on XC4000XL 0.35 m SRAM process for XC4000XL Product Obsolete or Under Obsolescence R XC4000E and XC4000X Series Field Programmable Gate Arrays much as 50% from XC4000 values. See Fast Carry Logic XC4000E and XC4000X Series on page 18 for more information. Compared to the XC4000 Select-RAM Memory: Edge-Triggered, Synchro- For readers already familiar with the XC4000 family of Xil- nous RAM Modes inx Field Programmable Gate Arrays, the major new fea- tures in the XC4000 Series devices are listed in this The RAM in any CLB can be congured for synchronous, section. The biggest advantages of XC4000E and edge-triggered, write operation. The read operation is not XC4000X devices are signicantly increased system affected by this change to an edge-triggered write. speed, greater capacity, and new architectural features, Dual-Port RAM particularly Select-RAM memory. The XC4000X devices also offer many new routing features, including special A separate option converts the 16x2 RAM in any CLB into a high-speed clock buffers that can be used to capture input 16x1 dual-port RAM with simultaneous Read/Write. data with minimal delay. The function generators in each CLB can be congured as Any XC4000E device is pinout- and bitstream-compatible either level-sensitive (asynchronous) single-port RAM, with the corresponding XC4000 device. An existing edge-triggered (synchronous) single-port RAM, edge-trig- XC4000 bitstream can be used to program an XC4000E gered (synchronous) dual-port RAM, or as combinatorial device. However, since the XC4000E includes many new logic. features, an XC4000E bitstream cannot be loaded into an Congurable RAM Content XC4000 device. XC4000X Series devices are not bitstream-compatible with The RAM content can now be loaded at conguration time, equivalent array size devices in the XC4000 or XC4000E so that the RAM starts up with user-dened data. families. However, equivalent array size devices, such as H Function Generator the XC4025, XC4025E, XC4028EX, and XC4028XL, are 6 pinout-compatible. In current XC4000 Series devices, the H function generator is more versatile than in the original XC4000. Its inputs can Improvements in XC4000E and XC4000X come not only from the F and G function generators but also from up to three of the four control input lines. The H Increased System Speed function generator can thus be totally or partially indepen- XC4000E and XC4000X devices can run at synchronous dent of the other two function generators, increasing the system clock rates of up to 80 MHz, and internal perfor- maximum capacity of the device. mance can exceed 150 MHz. This increase in performance IOB Clock Enable over the previous families stems from improvements in both device processing and system architecture. XC4000 The two ip-ops in each IOB have a common clock enable Series devices use a sub-micron multi-layer metal process. input, which through conguration can be activated individ- In addition, many architectural improvements have been ually for the input or output ip-op or both. This clock made, as described below. enable operates exactly like the EC pin on the XC4000 CLB. This new feature makes the IOBs more versatile, and The XC4000XL family is a high performance 3.3V family avoids the need for clock gating. based on 0.35 SRAM technology and supports system speeds to 80 MHz. Output Drivers PCI Compliance The output pull-up structure defaults to a TTL-like totem-pole. This driver is an n-channel pull-up transistor, XC4000 Series -2 and faster speed grades are fully PCI pulling to a voltage one transistor threshold below Vcc, just compliant. XC4000E and XC4000X devices can be used to like the XC4000 family outputs. Alternatively, XC4000 implement a one-chip PCI solution. Series devices can be globally congured with CMOS out- Carry Logic puts, with p-channel pull-up transistors pulling to Vcc. Also, the congurable pull-up resistor in the XC4000 Series is a The speed of the carry logic chain has increased dramati- p-channel transistor that pulls to Vcc, whereas in the origi- cally. Some parameters, such as the delay on the carry nal XC4000 family it is an n-channel transistor that pulls to chain through a single CLB (TBYP), have improved by as a voltage one transistor threshold below Vcc. May 14, 1999 (Version 1.6) 6-7