0 R Virtex-4 Family Overview 00 DS112 (v3.1) August 30, 2010 Product Specification General Description Combining Advanced Silicon Modular Block (ASMBL) architecture with a wide variety of flexible features, the Virtex-4 family from Xilinx greatly enhances programmable logic design capabilities, making it a powerful alternative to ASIC technology. Virtex-4 FPGAs comprise three platform familiesLX, FX, and SXoffering multiple feature choices and combinations to address all complex applications. The wide array of Virtex-4 FPGA hard-IP core blocks includes the PowerPC processors (with a new APU interface), tri-mode Ethernet MACs, 622 Mb/s to 6.5 Gb/s serial transceivers, dedicated DSP slices, high-speed clock management circuitry, and source-synchronous interface blocks. The basic Virtex-4 FPGA building blocks are enhancements of those found in the popular Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Virtex-II Pro X product families, so previous-generation designs are upward compatible. Virtex-4 devices are produced on a state-of-the-art 90 nm copper process using 300 mm (12-inch) wafer technology. Summary of Virtex-4 Family Features Three Families LX/SX/FX SelectIO Technology - Virtex-4 LX: High-performance logic applications solution - 1.5V to 3.3V I/O operation - Virtex-4 SX: High-performance solution for digital signal - Built-in ChipSync source-synchronous technology processing (DSP) applications - Digitally controlled impedance (DCI) active termination - Virtex-4 FX: High-performance, full-featured solution for - Fine grained I/O banking (configuration in one bank) embedded platform applications Flexible Logic Resources Xesium Clock Technology Secure Chip AES Bitstream Encryption - Digital clock manager (DCM) blocks 90 nm Copper CMOS Process - Additional phase-matched clock dividers (PMCD) - Differential global clocks 1.2V Core Voltage XtremeDSP Slice Flip-Chip Packaging including Pb-Free Package - 18 x 18, twos complement, signed Multiplier Choices - Optional pipeline stages RocketIO 622 Mb/s to 6.5 Gb/s Multi-Gigabit - Built-in Accumulator (48-bit) and Adder/Subtracter Transceiver (MGT) FX only Smart RAM Memory Hierarchy IBM PowerPC RISC Processor Core FX only - Distributed RAM - Dual-port 18-Kbit RAM blocks - PowerPC 405 (PPC405) Core Optional pipeline stages - Auxiliary Processor Unit Interface (User Coprocessor) Optional programmable FIFO logic automatically Multiple Tri-Mode Ethernet MACs FX only remaps RAM signals as FIFO signals - High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II. Table 1: Virtex-4 FPGA Family Members (1) Block RAM Configurable Logic Blocks (CLBs) Max Max PowerPC RocketIO Total Max (3) Array Logic Distributed XtremeDSP 18 Kb Block Processor Ethernet Transceiver I/O User (2) Device DCMs PMCDs Row x Col Cells Slices RAM (Kb) Slices Blocks RAM (Kb) Blocks MACs Blocks Banks I/O XC4VLX15 64 x 24 13,824 6,144 96 32 48 864 4 0 N/A N/A N/A 9 320 XC4VLX25 96 x 28 24,192 10,752 168 48 72 1,296 8 4 N/A N/A N/A 11 448 XC4VLX40 128 x 36 41,472 18,432 288 64 96 1,728 8 4 N/A N/A N/A 13 640 XC4VLX60 128 x 52 59,904 26,624 416 64 160 2,880 8 4 N/A N/A N/A 13 640 XC4VLX80 160 x 56 80,640 35,840 560 80 200 3,600 12 8 N/A N/A N/A 15 768 XC4VLX100 192 x 64 110,592 49,152 768 96 240 4,320 12 8 N/A N/A N/A 17 960 XC4VLX160 192 x 88 152,064 67,584 1056 96 288 5,184 12 8 N/A N/A N/A 17 960 XC4VLX200 192 x 116 200,448 89,088 1392 96 336 6,048 12 8 N/A N/A N/A 17 960 Copyright 20042010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. All other trademarks are the property of their respective owners. DS112 (v3.1) August 30, 2010 www.xilinx.com Product Specification 1R Virtex-4 Family Overview Table 1: Virtex-4 FPGA Family Members (Continued) (1) Configurable Logic Blocks (CLBs) Block RAM Max Max PowerPC RocketIO Total Max (3) Array Logic Distributed XtremeDSP 18 Kb Block Processor Ethernet Transceiver I/O User (2) Device Row x Col Cells Slices RAM (Kb) Slices Blocks RAM (Kb) DCMs PMCDs Blocks MACs Blocks Banks I/O 128 XC4VSX25 64 x 40 23,040 10,240 160 128 2,304 4 0 N/A N/A N/A 9 320 192 XC4VSX35 96 x 40 34,560 15,360 240 192 3,456 8 4 N/A N/A N/A 11 448 512 XC4VSX55 128 x 48 55,296 24,576 384 320 5,760 8 4 N/A N/A N/A 13 640 32 XC4VFX12 64 x 24 12,312 5,472 86 36 648 4 0 1 2 N/A 9 320 32 XC4VFX20 64 x 36 19,224 8,544 134 68 1,224 4 0 1 2 8 9 320 48 XC4VFX40 96 x 52 41,904 18,624 291 144 2,592 8 4 2 4 12 11 448 128 XC4VFX60 128 x 52 56,880 25,280 395 232 4,176 12 8 2 4 16 13 576 160 XC4VFX100 160 x 68 94,896 42,176 659 376 6,768 12 8 2 4 20 15 768 192 XC4VFX140 192 x 84 142,128 63,168 987 552 9,936 20 8 2 4 24 17 896 Notes: 1. One CLB = Four Slices = Maximum of 64 bits. 2. Each XtremeDSP slice contains one 18 x 18 multiplier, an adder, and an accumulator 3. Some of the row/column array is used by the processors in the FX devices. System Blocks Common to All Virtex-4 Families Xesium Clock Technology 500 MHz XtremeDSP Slices Dedicated 18-bit x 18-bit multiplier, Up to twenty Digital Clock Manager (DCM) modules multiply-accumulator, or multiply-adder blocks - Precision clock deskew and phase shift Optional pipeline stages for enhanced performance - Flexible frequency synthesis Optional 48-bit accumulator for multiply accumulate - Dual operating modes to ease performance trade-off decisions (MACC) operation - Improved maximum input/output frequency Integrated adder for complex-multiply or multiply-add - Improved phase shifting resolution operation - Reduced output jitter Cascadeable Multiply or MACC - Low-power operation Up to 100% speed improvement over previous - Enhanced phase detectors generation devices. - Wide phase shift range Companion Phase-Matched Clock Divider (PMCD) 500 MHz Integrated Block Memory blocks Up to 10 Mb of integrated block memory Differential clocking structure for optimized low-jitter Optional pipeline stages for higher performance clocking and precise duty cycle Multi-rate FIFO support logic 32 Global Clock networks - Full and Empty Flag support - Fully programmable AF and AE Flags Regional I/O and Local clocks - Synchronous/ Asynchronous Operation Dual-port architecture Flexible Logic Resources Independent read and write port width selection (RAM Up to 40% speed improvement over previous only) generation devices 18 Kbit blocks (memory and parity/sideband memory Up to 200,000 logic cells including: support) - Up to 178,176 internal registers with clock enable Configurations from 16K x 1 to 512 x 36 (XC4VLX200) (4K x 4 to 512 x 36 for FIFO operation) - Up to 178,176 look-up tables (LUTs) - Logic expanding multiplexers and I/O registers Byte-write capability (connection to PPC405, etc.) Cascadable variable shift registers or distributed Dedicated cascade routing to form 32K x 1 memory memory capability without using FPGA routing Up to 100% speed improvement over previous generation devices. DS112 (v3.1) August 30, 2010 www.xilinx.com Product Specification 2