11 Spartan-6 Family Overview DS160 (v2.0) October 25, 2011 Product Specification General Description The Spartan-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input look- up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO technology, power- optimized high-speed serial transceiver blocks, PCI Express compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low- cost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins. Summary of Spartan-6 FPGA Features Spartan-6 Family: Integrated Memory Controller blocks Spartan-6 LX FPGA: Logic optimized DDR, DDR2, DDR3, and LPDDR support Spartan-6 LXT FPGA: High-speed serial connectivity Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth) Multi-port bus structure with independent FIFO to reduce Designed for low cost design timing issues Multiple efficient integrated blocks Abundant logic resources with increased logic capacity Optimized selection of I/O standards Staggered pads Optional shift register or distributed RAM support High-volume plastic wire-bonded packages Efficient 6-input LUTs improve performance and minimize power Low static and dynamic power LUT with dual flip-flops for pipeline centric applications 45 nm process optimized for cost and low power Block RAM with a wide range of granularity Hibernate power-down mode for zero power Suspend mode maintains state and configuration with Fast block RAM with byte write enable multi-pin wake-up, control enhancement 18 Kb blocks that can be optionally programmed as two Lower-power 1.0V core voltage (LX FPGAs, -1L only) independent 9 Kb block RAMs High performance 1.2V core voltage (LX and LXT Clock Management Tile (CMT) for enhanced performance FPGAs, -2, -3, and -3N speed grades) Low noise, flexible clocking Multi-voltage, multi-standard SelectIO interface banks Digital Clock Managers (DCMs) eliminate clock skew Up to 1,080 Mb/s data transfer rate per differential I/O and duty cycle distortion Selectable output drive, up to 24 mA per pin Phase-Locked Loops (PLLs) for low-jitter clocking 3.3V to 1.2V I/O standards and protocols Frequency synthesis with simultaneous multiplication, Low-cost HSTL and SSTL memory interfaces division, and phase shifting Hot swap compliance Sixteen low-skew global clock networks Adjustable I/O slew rates to improve signal integrity Simplified configuration, supports low-cost standards High-speed GTP serial transceivers in the LXT FPGAs 2-pin auto-detect configuration Up to 3.2 Gb/s Broad third-party SPI (up to x4) and NOR flash support High-speed interfaces including: Serial ATA, Aurora, Feature rich Xilinx Platform Flash with JTAG 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, MultiBoot support for remote upgrade with multiple GPON, DisplayPort, and XAUI bitstreams, using watchdog protection Integrated Endpoint block for PCI Express designs (LXT) Enhanced security for design protection Low-cost PCI technology support compatible with the Unique Device DNA identifier for design authentication 33 MHz, 32- and 64-bit specification. AES bitstream encryption in the larger devices Faster embedded processing with enhanced, low cost, Efficient DSP48A1 slices MicroBlaze soft processor High-performance arithmetic and signal processing Industry-leading IP and reference designs Fast 18 x 18 multiplier and 48-bit accumulator Pipelining and cascading capability Pre-adder to assist filter applications 20092011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS160 (v2.0) October 25, 2011 www.xilinx.com Product Specification 1Spartan-6 Family Overview Spartan-6 FPGA Feature Summary Table 1: Spartan-6 FPGA Feature Summary by Device Configurable Logic Blocks (CLBs) Block RAM Blocks Memory Endpoint Maximum Total Max Logic DSP48A1 Controller (5) Device Max CMTs Blocks for GTP I/O User (1) (3) Cells Slices Blocks (2) (4) Slices Flip-Flops Distributed 18 Kb Max (Kb) PCI Express Transceivers Banks I/O (6) (Max) RAM (Kb) XC6SLX4 3,840 600 4,800 75 8 12 216 2 0 0 0 4 132 XC6SLX9 9,152 1,430 11,440 90 16 32 576 2 2 0 0 4 200 XC6SLX16 14,579 2,278 18,224 136 32 32 576 2 2 0 0 4 232 XC6SLX25 24,051 3,758 30,064 229 38 52 936 2 2 0 0 4 266 XC6SLX45 43,661 6,822 54,576 401 58 116 2,088 4 2 0 0 4 358 XC6SLX75 74,637 11,662 93,296 692 132 172 3,096 6 4 0 0 6 408 XC6SLX100 101,261 15,822 126,576 976 180 268 4,824 6 4 0 0 6 480 XC6SLX150 147,443 23,038 184,304 1,355 180 268 4,824 6 4 0 0 6 576 XC6SLX25T 24,051 3,758 30,064 229 38 52 936 2 2 1 2 4 250 XC6SLX45T 43,661 6,822 54,576 401 58 116 2,088 4 2 1 4 4 296 XC6SLX75T 74,637 11,662 93,296 692 132 172 3,096 6 4 1 8 6 348 XC6SLX100T 101,261 15,822 126,576 976 180 268 4,824 6 4 1 8 6 498 XC6SLX150T 147,443 23,038 184,304 1,355 180 268 4,824 6 4 1 8 6 540 Notes: 1. Spartan-6 FPGA logic cell ratings reflect the increased logic cell capability offered by the new 6-input LUT architecture. 2. Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops. 3. Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator. 4. Block RAMs are fundamentally 18 Kb in size. Each block can also be used as two independent 9 Kb blocks. 5. Each CMT contains two DCMs and one PLL. 6. Memory Controller Blocks are not supported in the -3N speed grade. DS160 (v2.0) October 25, 2011 www.xilinx.com Product Specification 2