Zynq-7000 SoC Data Sheet: Overview DS190 (v1.11.1) July 2, 2018 Product Specification Zynq-7000 SoC First Generation Architecture The Zynq-7000 family is based on the Xilinx SoC architecture. These products integrate a feature-rich dual-core or single-core ARM Cortex-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. Processing System (PS) ARM Cortex-A9 Based I/O Peripherals and Interfaces Application Processor Unit (APU) Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std 802.3 and IEEE Std 1588 revision 2.0 support 2.5 DMIPS/MHz per CPU Scatter-gather DMA capability CPU frequency: Up to 1 GHz Recognition of 1588 rev. 2 PTP frames Coherent multiprocessor support GMII, RGMII, and SGMII interfaces ARMv7-A architecture Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints TrustZone security USB 2.0 compliant device IP core Thumb-2 instruction set Supports on-the-go, high-speed, full-speed, and low-speed Jazelle RCT execution Environment Architecture modes NEON media-processing engine Intel EHCI compliant USB host Single and double precision Vector Floating Point Unit (VFPU) 8-bit ULPI external PHY interface CoreSight and Program Trace Macrocell (PTM) Two full CAN 2.0B compliant CAN bus interfaces Timer and Interrupts CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard Three watchdog timers compliant One global timer External PHY interface Two triple-timer counters Two SD/SDIO 2.0/MMC3.31 compliant controllers Caches Two full-duplex SPI ports with three peripheral chip selects 32 KB Level 1 4-way set-associative instruction and data caches Two high-speed UARTs (up to 1 Mb/s) (independent for each CPU) Two master and slave I2C interfaces 512 KB 8-way set-associative Level 2 cache GPIO with four 32-bit banks, of which up to 54 bits can be used with (shared between the CPUs) the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits Byte-parity support (up to two banks of 32b) connected to the Programmable Logic Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignments On-Chip Memory Interconnect On-chip boot ROM 256 KB on-chip RAM (OCM) High-bandwidth connectivity within PS and between PS and PL Byte-parity support ARM AMBA AXI based QoS support on critical masters for latency and bandwidth control External Memory Interfaces Multiprotocol dynamic memory controller 16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 memories ECC support in 16-bit mode 1GB of address space using single rank of 8-, 16-, or 32-bit-wide memories Static memory interfaces 8-bit SRAM data bus with up to 64 MB support Parallel NOR flash support ONFI1.0 NAND flash support (1-bit ECC) 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit) serial NOR flash 8-Channel DMA Controller Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction support Copyright 20122018 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM Cortex-A9, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners. DS190 (v1.11.1) July 2, 2018 www.xilinx.com Product Specification 1Zynq-7000 SoC Data Sheet: Overview JTAG Boundary-Scan Programmable Logic (PL) IEEE Std 1149.1 Compatible Test Interface Configurable Logic Blocks (CLB) PCI Express Block Look-up tables (LUT) Flip-flops Supports Root complex and End Point configurations Cascadeable adders Supports up to Gen2 speeds Supports up to 8 lanes 36 Kb Block RAM Serial Transceivers True Dual-Port Up to 72 bits wide Up to 16 receivers and transmitters Configurable as dual 18 Kb block RAM Supports up to 12.5 Gb/s data rates DSP Blocks Two 12-Bit Analog-to-Digital Converters 18 x 25 signed multiply On-chip voltage and temperature sensing 48-bit adder/accumulator Up to 17 external differential input channels 25-bit pre-adder One million samples per second maximum conversion rate Programmable I/O Blocks Supports LVCMOS, LVDS, and SSTL 1.2V to 3.3V I/O Programmable I/O delay and SerDes Feature Summary Table 1: Zynq-7000 and Zynq-7000S SoCs Device Name Z-7007S Z-7012S Z-7014S Z-7010 Z-7015 Z-7020 Z-7030 Z-7035 Z-7045 Z-7100 Part Number XC7Z007S XC7Z012S XC7Z014S XC7Z010 XC7Z015 XC7Z020 XC7Z030 XC7Z035 XC7Z045 XC7Z100 Processor Core Single-core ARM Cortex-A9 Dual-core ARM Cortex-A9 MPCore with CoreSight MPCore with CoreSight Processor Extensions NEON & Single / Double Precision Floating Point for each processor Maximum Frequency 667 MHz (-1) 766 MHz (-2) 667 MHz (-1) 766 MHz (-2) 866 MHz (-3) 667 MHz (-1) 800 MHz (-2) 1 GHz (-3) 667 MHz (-1) 800 MHz (-2) L1 Cache 32 KB Instruction, 32 KB data per processor L2 Cache 512 KB On-Chip Memory 256 KB External Memory DDR3, DDR3L, DDR2, LPDDR2 (1) Support External Static Memory 2x Quad-SPI, NAND, NOR (1) Support DMA Channels 8 (4 dedicated to Programmable Logic) (1) Peripherals 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO Peripherals w/ 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO (1) built-in DMA (2) Security RSA Authentication, and AES and SHA 256-bit Decryption and Authentication for Secure Boot 2x AXI 32b Master 2x AXI 32-bit Slave Processing System to Programmable Logic 4x AXI 64-bit/32-bit Memory Interface Ports (Primary Interfaces & AXI 64-bit ACP Interrupts Only) 16 Interrupts DS190 (v1.11.1) July 2, 2018 www.xilinx.com Product Specification 2 Processing System