0 R XC95144XL High Performance CPLD 00 DS056 (v2.0) April 3, 2007 Product Specification 54V18 Function Blocks, providing 3,200 usable gates with Features propagation delays of 5 ns. See Figure 2 for overview. 5 ns pin-to-pin logic delays Power Estimation System frequency up to 178 MHz 144 macrocells with 3,200 usable gates Power dissipation in CPLDs can vary substantially depend- Available in small footprint packages ing on the system frequency, design application and output - 100-pin TQFP (81 user I/O pins) loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power - 144-pin TQFP (117 user I/O pins) mode (from the default high-performance mode). In addi- - 144-CSP (117 user I/O pins) tion, unused product-terms and macrocells are automati- - Pb-free available for all packages cally deactivated by the software to further conserve power. Optimized for high-performance 3.3V systems - Low power operation For a general estimate of I , the following equation may be CC - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V used: signals I (mA) = MC (0.175*PT + 0.345) + MC (0.052*PT CC HS HS LP LP - 3.3V or 2.5V output capability + 0.272) + 0.04 * MC (MC +MC )* f TOG HS LP - Advanced 0.35 micron feature size CMOS where: Fast FLASH technology MC = macrocells in high-speed configuration HS Advanced system features PT = average number of high-speed product terms HS - In-system programmable per macrocell - Superior pin-locking and routability with MC = macrocells in low power configuration LP Fast CONNECT II switch matrix PT = average number of low power product terms per LP - Extra wide 54-input Function Blocks macrocell - Up to 90 product-terms per macrocell with f = maximum clock frequency individual product-term allocation MCTOG = average % of flip-flops toggling per clock - Local clock inversion with three global and one (~12%) product-term clocks This calculation was derived from laboratory measurements - Individual output enable per output pin with local of an XC9500XL part filled with 16-bit counters and allowing inversion a single output (the LSB) to be enabled. The actual I CC - Input hysteresis on all user and boundary-scan pin value varies with the design application and should be veri- inputs fied during normal system operation. Figure 1 shows the - Bus-hold circuitry on all user pin inputs above estimation in a graphical form. For a more detailed - Full IEEE Standard 1149.1 boundary-scan (JTAG) discussion of power consumption in this device, see Xilinx Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V Pin-compatible with 5V-core XC95144 device in the 100-pin TQFP package WARNING: Programming temperature range of T = 0 C to +70 C A Description The XC95144XL is a 3.3V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems. It is comprised of eight 1998-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at R XC95144XL High Performance CPLD application note XAPP114, Understanding XC9500XL CPLD Power. 250 178 MHz 200 150 104 MHz 100 50 0 50 100 150 200 Clock Frequency (MHz) Figure 1: Typical I vs. Frequency for XC95144XL CC 2 www.xilinx.com DS056 (v2.0) April 3, 2007 Product Specification Low Power High Performance Typical I (mA) CC