8 8 R Platform Flash XL High-Density Configuration and Storage Device DS617 (v4.1) January 13, 2021 Product Specification Features In-System Programmable Flash Memory Optimized for Memory Organization Virtex-5 or Virtex-6 FPGA Configuration 128-Mb Main Array Capacity High-Performance FPGA Bitstream Transfer up to 16-bit Data Bus 800 Mb/s (50 MHz 16-bits), Ideal for Multiple 8-Mb Bank Architecture for Dual PCI Express Endpoint Applications Erase/Program and Read Operation MultiBoot Bitstream, Design Revision Storage 127 Regular 1-Mb Main Blocks FPGA Configuration Synchronization (READY WAIT) 4 Small 256-Kb Parameter Blocks Handshake Signal Synchronous/Asynchronous Read Modes ISE Software Support for In-System Programming via Xilinx JTAG Cables Power-On in Synchronous Burst Read Mode Standard NOR-Flash Interface for Access to Code or Asynchronous Random Access Mode Data Storage Accelerated Asynchronous Page Read Mode Operation over Full Industrial Temperature Range Protection (40C to +85C) Default Block Protection at Power-Up Common Flash Interface (CFI) Hardware Write Protection (when V = V ) Low-Power Advanced CMOS NOR-Flash Process PP SS Security Endurance of 10,000 Program/Erase Cycles Per Block Unique Device Number (64-bits) Power Supplies One-Time-Programmable (OTP) Registers Industry-Standard Core Power Supply Voltage (V ) = 1.8V DD Small-Footprint (10 mm 13 mm) FT64 Packaging 3.3V or 2.5V I/O (V ) Power Supply Voltage DDQ Description A reliable compact high-performance configuration Platform Flash XL is a non-volatile flash storage solution, bitstream storage and delivery solution is essential for the optimized for FPGA configuration. The device provides a high-density FPGAs. Platform Flash XL is the industry s READY WAIT signal that synchronizes the start of the FPGA highest performing configuration and storage device and is configuration process, improving both system reliability and specially optimized for high-performance FPGA simplifying board design. Platform Flash XL can download an configuration. Platform Flash XL integrates 128 Mb of XC5VLX330 bitstream (79,704,832 bits) in less than 100 ms, in-system programmable flash storage and performance making the configuration performance of Platform Flash XL features for configuration within a small-footprint FT64 ideal for PCI Express endpoints and other high-performance package (Figure 5). Power-on burst read mode and applications. dedicated I/O power supply enable Platform Flash XL to mate seamlessly with the native SelectMAP configuration Platform Flash XL is a single-chip configuration solution with interface. A wide, 16-bit data bus delivers the FPGA additional system-level capabilities. A standard NOR flash configuration bitstream at speeds up to 800 Mb/s without interface (Figure 2) and support for common flash interface wait states. See UG438, Platform Flash XL Configuration (CFI) queries provide industry-standard access to the device and Storage Device User Guide, for system-level usage and memory space. The Platform Flash XL s 128 Mb capacity can performance considerations. typically hold one or more FPGA bitstreams. Any memory space not used for bitstream storage can be used to hold Platform Flash XL is supported for use with Virtex-5 or Virtex-6 general purpose data or embedded processor code. FPGAs only. Use with older Virtex families, Spartan families, or AES encrypted bitstreams is not supported. Copyright 20072021 Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS617 (v4.1) January 13, 2021 www.xilinx.com Send Feedback Product Specification 1R Platform Flash XL High-Density Configuration and Storage Device X-Ref Target - Figure 1 Platform Flash XL FPGA Configuration Synchronization Handshake READY WAIT (1) Clock up to 50 MHz FPGA Design Wide (16-bit) Datapath (.bit) File Up to 800 Mb/s DS617 01 102709 Notes: 1. System considerations can lower the configuration clock frequency below the maximum clock frequency for the device. To determine the maximum configuration clock frequency, check the minimum clock period (T ) for the chosen I/O voltage range (V ), the clock High- KHKH DDQ to-output valid time (T ), and the FPGA SelectMAP setup time. KHQV Figure 1: Platform Flash XL Delivers Reliable, High-Performance FPGA Configuration X-Ref Target - Figure 2 Platform Flash XL support is integrated with the Xilinx design and debug tool suite.The iMPACT application, Platform Flash XL FPGA included with the ISE software, supports indirect, in-system programming of Platform Flash XL via the IEEE Standard Code Control 1149.1 (JTAG) port on the FPGA for prototype programming Address (Figure 3). User Data User Design Data/Commands Design (.bit) File, Rev. 1 Design (.bit) File, Rev. 0 DS617 02 081209 Figure 2: Standard NOR Flash Interface for User Access to Memory X-Ref Target - Figure 3 Single Cable Connector for Direct FPGA Configuration/Debug and Indirect Platform Flash XL Programming FPGA Xilinx JTAG For Programming Cable Connector Platform Flash XL Indirect, Platform Flash XL In-System Programming Engine Control FPGA Design (.bit) File For Programming Address Platform Flash XL Data/Commands DS617 03 081209 Figure 3: Indirect Programming Solution for Platform Flash XL DS617 (v4.1) January 13, 2021 www.xilinx.com Send Feedback Product Specification 2 Standard NOR Flash Interface BPI Flash IEEE 1149.1 Configuration Port (JTAG) Port SelectMAP (x16) Port