0 R CoolRunner XPLA3 CPLD 014 DS012 (v2.5) May 26, 2009 Product Specification Available in commercial grade and extended voltage Features (2.7V to 3.6V) industrial grade Fast Zero Power (FZP) design technique provides 5V tolerant I/O pins ultra-low power and very high speed Input register setup time of 2.5 ns - Typical Standby Current of 17 to 18 A at 25C Single pass logic expandable to 48 product terms Innovative CoolRunner XPLA3 architecture High-speed pin-to-pin delays of 5.0 ns combines high speed with extreme flexibility Slew rate control per output Based on industry s first TotalCMOS PLD both 100% routable CMOS design and process technologies Security bit prevents unauthorized access Advanced 0.35 five layer metal EEPROM process Supports hot-plugging capability - 1,000 erase/program cycles guaranteed Design entry/verification using Xilinx or industry - 20 years data retention guaranteed standard CAE tools 3V, In-System Programmable (ISP) using JTAG IEEE Innovative Control Term structure provides: 1149.1 interface - Asynchronous macrocell clocking - Full Boundary-Scan Test (IEEE 1149.1) - Asynchronous macrocell register preset/reset - Fast programming times - Clock enable control per macrocell Support for complex asynchronous clocking Four output enable controls per function block - 16 product term clocks and four local control term Foldback NAND for synthesis optimization clocks per function block Universal 3-state which facilitatesbed of nail testing - Four global clocks and one universal control term Available in Chip-scale BGA, Fineline BGA, and QFP clock per device packages. Pb-free available for most package types. Excellent pin retention during design changes See Xilinx Packaging for more information. Table 1: CoolRunner XPLA3 Device Family XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL Macrocells 32 64 128 256 384 512 Usable Gates 750 1,500 3,000 6,000 9,000 12,000 Registers 32 64 128 256 384 512 T(ns) 4.55.5 5.57.0 7.0 7.0 PD T (ns) 3.0 3.5 3.5 4.3 4.3 3.8 SU T (ns) 3.5 4 4 4.5 4.5 5.0 CO F (MHz) 213 192 175 154 135 135 system I ( A) 17 17 17 18 18 18 CCSB Table 2: CoolRunner XPLA3 Packages and User I/O Pins XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL XCR3512XL 44-pin VQFP 36 36 - - - - 48-pin 0.8mm CSP 36 40 - - - - 56-pin 0.5mm CSP - 48 - - - - 100-pin VQFP - 68 84 - - - 144-pin 0.8mm CSP - - 108 - - - (1) 144-pin TQFP - - 108 120 118 - 208-pin PQFP - - - 164 172 180 256-pin Fineline BGA - - - 164 212 212 280-pin 0.8mm CSP - - - 164 - - 324-pin Fineline BGA - - - - 220 260 1. XCR3384XL TQ144 JTAG pins are not compatible with other members of the CoolRunner XPLA3 family in the TQ144 package. 2. Most packages are available in Pb-Free option. See individual data sheets for more details. 3. The 44-pin PLCC package is discontinued per XCN07022. 20002009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. DS012 (v2.5) May 26, 2009 www.xilinx.com 1 Product SpecificationR CoolRunner XPLA3 CPLD Interconnect Array (ZIA). The ZIA is a virtual crosspoint Family Overview switch. Each function block has 40 inputs from the ZIA and The CoolRunner XPLA3 (eXtended Programmable Logic contains 16 macrocells. Array) family of CPLDs is targeted for low power systems From this point of view, this architecture looks like many that include portable, handheld, and power sensitive appli- other CPLD architectures. What makes the CoolRunner cations. Each member of the CoolRunner XPLA3 family XPLA3 family unique is logic allocation inside each function includes Fast Zero Power (FZP) design technology that block, and the design technique used to implement product combines low power and high speed. With this design tech- terms. nique, the CoolRunner XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while simultaneously delivering power Function Block Architecture that is less than 56 W at standby without the need forturbo bit or other power down schemes. By replacing Figure 3 illustrates the function block architecture. Each conventional sense amplifier methods for implementing function block contains a PLA array that generates control product terms (a technique that has been used in PLDs terms, clock terms, and logic cells. A PLA differs from a PAL since the bipolar era) with a cascaded chain of pure CMOS in that the PLA has a fully programmable AND array fol- gates, the dynamic power is also substantially lower than lowed by a fully programmable OR array. A PAL array has a any other CPLD. CoolRunner devices are the only TotalC- fixed OR array, limiting flexibility. Refer to Figure 2 for an MOS PLDs, as they use both a CMOS process technology example of a PAL and a PLA array. The PLA array receives and the patented full CMOS FZP design technique. The its inputs directly from the ZIA. There are 40 pairs of true FZP design technique combines fast nonvolatile memory and complement inputs from the ZIA that feed the 48 prod- cells with ultra-low power SRAM shadow memory to deliver uct terms in the array. Within the 48 P-terms there are eight the industrys lowest power 3.3V CPLD family. local control terms (LCT 0:7 ) available as control signals to each macrocell for use as asynchronous clocks, resets, pre- The CoolRunner XPLA3 family employs a full PLA structure sets and output enables. If not needed as control terms, for logic allocation within a function block. The PLA provides these P-Terms can join the other 40 P-Terms as additional maximum flexibility and logic density, with superior pin lock- logic resources. ing capability, while maintaining deterministic timing. In each function block there are eight foldback NAND prod- CoolRunner XPLA3 CPLDs are supported by uct terms that can be used to synthesize increased logic Xilinx WebPACK software and industry standard CAE density in support of wider logic equations. This feature can tools (Mentor, Cadence/OrCAD, Exemplar Logic, Synopsys, be disabled in software by the user. As with unused control Viewlogic, and Synplicity), using HDL editors with ABEL, P-Terms, unused foldback NAND P-Terms can be used as VHDL, and Verilog, and/or schematic capture design entry. additional logic resources. Design verification uses industry standard simulators for functional and timing simulation. Development is supported Sixteen high-speed P-Terms are available at each macro- on multiple personal computer (PC), Sun, and HP plat- cell for speed critical logic. If wider than a single P-Term forms. logic is required at a macrocell, 47 additional P-Terms can be summed in prior to the VFM (Variable Function Multi- The CoolRunner XPLA3 family features also include the plexer). The VFM increases logic optimization by imple- industry-standard, IEEE 1149.1, JTAG interface through menting some two input logic functions before entering the which boundary-scan testing, In-System Programming macrocell (see Figure 4). (ISP), and reprogramming of the device can occur. The CoolRunner XPLA3 CPLD is electrically reprogrammable Each macrocell can support combinatorial or registered using industry standard device programmers. logic. The macrocell register accommodates asynchronous presets and resets, andpower o initial state. A hardware clock enable is also provided for either D or T type registers, CoolRunner XPLA3 Architecture and the register clock input is used as a latch enable when Figure 1 shows a high-level block diagram of a 128 macro- the macrocell register is configured as a latch function. cell device implementing the CoolRunner XPLA3 architec- ture. The CoolRunner XPLA3 architecture consists of function blocks that are interconnected by a Zero-power 2 www.xilinx.com DS012 (v2.5) May 26, 2009 Product Specification