Zynq UltraScale+ MPSoC Data Sheet: Overview DS891 (v1.9) May 26, 2021 Product Specification General Description The Zynq UltraScale+ MPSoC family is based on the Xilinx UltraScale MPSoC architecture. This family of products integrates a feature-rich 64-bit quad-core or dual-core Arm Cortex-A53 and dual-core Arm Cortex-R5F based processing system (PS) and Xilinx programmable logic (PL) UltraScale architecture in a single device. Also included are on-chip memory, multiport external memory interfaces, and a rich set of peripheral connectivity interfaces. Processing System (PS) Arm Cortex-A53 Based Application Dual-core Arm Cortex-R5F Based Processing Unit (APU) Real-Time Processing Unit (RPU) Quad-core or dual-core CPU frequency: Up to 600MHz CPU frequency: Up to 1.5GHz Armv7-R Architecture Extendable cache coherency o A32/T32 instruction set Armv8-A Architecture Single/double precision Floating Point Unit (FPU) o 64-bit or 32-bit operating modes CoreSight and Embedded Trace Macrocell (ETM) o TrustZone security Lock-step or independent operation o A64 instruction set in 64-bit mode, A32/T32 instruction set in 32-bit mode Timer and Interrupts: NEON Advanced SIMD media-processing engine o One watchdog timer Single/double precision Floating Point Unit (FPU) o Two triple-timer counters CoreSight and Embedded Trace Macrocell (ETM) Caches and Tightly Coupled Memories (TCMs) Accelerator Coherency Port (ACP) o 32KB Level 1, 4-way set-associative instruction and data cache with ECC AXI Coherency Extension (ACE) (independent for each CPU) Power island gating for each processor core o 128KB TCM with ECC (independent for each Timer and Interrupts CPU) that can be combined to become 256KB o Arm Generic timers support in lockstep mode o Two system level triple-timer counters o One watchdog timer On-Chip Memory o One global system timer 256KB on-chip RAM (OCM) in PS with ECC Caches Up to 36Mb on-chip RAM (UltraRAM) with ECC in o 32KB Level 1, 2-way set-associative PL instruction cache with parity (independent for Up to 35Mb on-chip RAM (block RAM) with ECC each CPU) in PL o 32KB Level 1, 4-way set-associative data Up to 11Mb on-chip RAM (distributed RAM) in PL cache with ECC (independent for each CPU) o 1MB 16-way set-associative Level 2 cache with ECC (shared between the CPUs) Copyright 20152021 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, Kintex, Spartan, Versal, Virtex, Vitis, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, Arm1176JZ-S, CoreSight, Cortex, PrimeCell, Mali, and MPCore are trademarks of Arm in the EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and are used under license. All other trademarks are the property of their respective owners. DS891 (v1.9) May 26, 2021 www.xilinx.com Product Specification 1Zynq UltraScale+ MPSoC Data Sheet: Overview Four 10/100/1000 tri-speed Ethernet MAC Arm Mali-400 Based GPU peripherals with IEEE Std 802.3 and IEEE Std 1588 Supports OpenGL ES 1.1 and 2.0 revision 2.0 support Supports OpenVG 1.1 o Scatter-gather DMA capability GPU frequency: Up to 667MHz o Recognition of IEEE Std 1588 rev.2 PTP frames Single Geometry Processor, Two Pixel Processors o GMII, RGMII, and SGMII interfaces o Jumbo frames Pixel Fill Rate: 2 Mpixels/sec/MHz Two USB 3.0/2.0 Device, Host, or OTG peripherals, Triangle Rate: 0.11 Mtriangles/sec/MHz each supporting up to 12 endpoints 64KB L2 Cache o USB 3.0/2.0 compliant device IP core Power island gating o Super-speed, high- speed, full-speed, and External Memory Interfaces low-speed modes o Intel XHCI- compliant USB host Multi-protocol dynamic memory controller Two full CAN 2.0B-compliant CAN bus interfaces 32-bit or 64-bit interfaces to DDR4, DDR3, o CAN 2.0-A and CAN 2.0-B and ISO 118981-1 DDR3L, or LPDDR3 memories, and 32-bit standard compliant interface to LPDDR4 memory Two SD/SDIO 2.0/eMMC4.51 compliant ECC support in 64-bit and 32-bit modes controllers Up to 32GB of address space using single or dual Two full-duplex SPI ports with three peripheral rank of 8-, 16-, or 32-bit-wide memories chip selects Static memory interfaces Two high-speed UARTs (up to 1Mb/s) o eMMC4.51 Managed NAND flash support Two master and slave I2C interfaces o ONFI3.1 NAND flash with 24-bit ECC Up to 78 flexible multiplexed I/O (MIO) (up to o 1-bit SPI, 2-bit SPI, 4-bit SPI (Quad-SPI), or three banks of 26 I/Os) for peripheral pin two Quad-SPI (8-bit) serial NOR flash assignment 8-Channel DMA Controller Up to 96 EMIOs (up to three banks of 32 I/Os) connected to the PL Two DMA controllers of 8-channels each Interconnect Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather High-bandwidth connectivity within PS transaction support and between PS and PL Arm AMBA AXI4-based Serial Transceivers QoS support for latency and bandwidth control Four dedicated PS-GTR receivers and Cache Coherent Interconnect (CCI) transmitters supports up to 6.0Gb/s data rates System Memory Management o Supports SGMII tri-speed Ethernet, PCI Express Gen2, Serial-ATA (SATA), USB3.0, System Memory Management Unit (SMMU) and DisplayPort Xilinx Memory Protection Unit (XMPU) Dedicated I/O Peripherals and Platform Management Unit Interfaces Power gates PS peripherals, power islands, and power domains PCI Express Compliant with PCIe 2.1 base specification Clock gates PS peripheral user firmware option o Root complex and End Point configurations Configuration and Security Unit o x1, x2, and x4 at Gen1 or Gen2 rates SATA Host Boots PS and configures PL o 1.5, 3.0, and 6.0Gb/s data rates as defined by Supports secure and non-secure boot modes SATA Specification, revision 3.1 System Monitor in PS o Supports up to two channels DisplayPort Controller On-chip voltage and temperature sensing o Up to 5.4Gb/s rate o Up to two TX lanes (no RX support) DS891 (v1.9) May 26, 2021 www.xilinx.com Product Specification 2