UltraScale Architecture and
Product Data Sheet: Overview
DS890 (v3.3) March 12, 2018 Preliminary Product Specification
General Description
Xilinx UltraScale architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of
system requirements with a focus on lowering total power consumption through numerous innovative technological
advancements.
Kintex UltraScale FPGAs: High-performance FPGAs with a focus on price/performance, using both monolithic and
next-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generation
transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.
Kintex UltraScale+ FPGAs: Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of
high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power
options that deliver the optimal balance between the required system performance and the smallest power envelope.
Virtex UltraScale FPGAs: High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI
technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and
application requirements through integration of various system-level functions.
Virtex UltraScale+ FPGAs: The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory
available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal
balance between the required system performance and the smallest power envelope.
Zynq UltraScale+ MPSoCs: Combine the ARM v8-based Cortex-A53 high-performance energy-efficient 64-bit application
processor with the ARM Cortex-R5 real-time processor and the UltraScale architecture to create the industry's first All
Programmable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration.
Zynq UltraScale+ RFSoCs: Combine RF data converter subsystem and forward error correction with industry-leading
programmable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft-decision FECs (SD-FEC)
provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.
Family Comparisons
Table 1: Device Resources
Kintex Kintex Virtex Virtex Zynq Zynq
UltraScale UltraScale+ UltraScale UltraScale+ UltraScale+ UltraScale+
FPGA FPGA FPGA FPGA MPSoC RFSoC
MPSoC Processing System
RF-ADC/DAC
SD-FEC
System Logic Cells (K) 3181,451 3561,143 7835,541 8623,780 1031,143 678930
Block Memory (Mb) 12.775.9 12.734.6 44.3132.9 23.694.5 4.534.6 27.838.0
UltraRAM (Mb) 036 90360 036 13.522.5
HBM DRAM (GB) 08
DSP (Slices) 7685,520 1,3683,528 6002,880 2,28012,288 2403,528 3,1454,272
DSP Performance (GMAC/s) 8,180 6,287 4,268 21,897 6,287 7,613
Transceivers 1264 1676 36120 32128 072 816
Max. Transceiver Speed (Gb/s) 16.3 32.75 30.5 58.0 32.75 32.75
Max. Serial Bandwidth (full duplex) (Gb/s) 2,086 3,268 5,616 8,384 3,268 1,048
Memory Interface Performance (Mb/s) 2,400 2,666 2,400 2,666 2,666 2,666
I/O Pins 312832 280668 3381,456 208832 82668 280408
Copyright 20132018 Xilinx, Inc., Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, UltraScale, Virtex, Vivado, Zynq, and other designated brands included herein are
trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, ARM, ARM1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of ARM in the
EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS890 (v3.3) March 12, 2018 www.xilinx.com
Preliminary Product Specification 1UltraScale Architecture and Product Data Sheet: Overview
Summary of Features
RF Data Converter Subsystem Overview
Most Zynq UltraScale+ RFSoCs include an RF data converter subsystem, which contains multiple radio
frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog
converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be
individually configured for real data or can be configured in pairs for real and imaginary I/Q data. The
12-bit RF-ADCs support sample rates up to 2.058GSPS or 4GSPS, depending on the selected device. The
14-bit RF-DACs support sample rates up to 6.554GSPS.
Soft Decision Forward Error Correction (SD-FEC) Overview
Some Zynq UltraScale+ RFSoCs include highly flexible soft-decision FEC blocks for decoding and encoding
data as a means to control errors in data transmission over unreliable or noisy communication channels.
The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in
5G wireless, backhaul, DOCSIS, and LTE applications.
Processing System Overview
Zynq UltraScale+ MPSoCs and RFSoCs feature dual and quad core variants of the ARM Cortex-A53 (APU)
with dual-core ARM Cortex-R5 (RPU) processing system (PS). Some devices also include a dedicated ARM
Mali-400 MP2 graphics processing unit (GPU). See Table 2.
Table 2: Zynq UltraScale+ MPSoC and RFSoC Device Features
MPSoC RFSoC
CG Devices EG Devices EV Devices DR Devices
APU Dual-core ARM Cortex-A53 Quad-core ARM Cortex-A53 Quad-core ARM Cortex-A53 Quad-core ARM Cortex-A53
RPU Dual-core ARM Cortex-R5 Dual-core ARM Cortex-R5 Dual-core ARM Cortex-R5 Dual-core ARM Cortex-R5
GPU Mali-400MP2 Mali-400MP2
VCU H.264/H.265
To support the processors' functionality, a number of peripherals with dedicated functions are included in
the PS. For interfacing to external memories for data or configuration storage, the PS includes a
multi-protocol dynamic memory controller, a DMA controller, a NAND controller, an SD/eMMC controller
and a Quad SPI controller. In addition to interfacing to external memories, the APU also includes a Level-1
(L1) and Level-2 (L2) cache hierarchy; the RPU includes an L1 cache and Tightly Coupled memory
subsystem. Each has access to a 256KB on-chip memory.
For high-speed interfacing, the PS includes 4 channels of transmit (TX) and receive (RX) pairs of
transceivers, called PS-GTR transceivers, supporting data rates of up to 6.0Gb/s. These transceivers can
interface to the high-speed peripheral blocks to support PCIe Gen2 root complex or end point in x1, x2, or
x4 configurations; Serial-ATA (SATA) at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s data rates; and up to two lanes of
Display Port at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s data rates. The PS-GTR transceivers can also interface to
components over USB 3.0 and Serial Gigabit Media Independent Interface (SGMII).
DS890 (v3.3) March 12, 2018 www.xilinx.com
Preliminary Product Specification 2