Doc. No. DSA3F4GH2340ABFF.02 A3F4GH20ABF/A3F4GH30ABF/A3F4GH40ABF 4Gb DDR4 SDRAM 4Gb DDR4 SDRAM Specification Features Operating case temperature range Power supply TC = 0C to +95C - VDD = VDDQ = 1.2V 5% Refresh cycles - VPP = 2.5V 5% + 10% Average refresh period Data rate 7.8s at 0C TC +85C - 2666Mbps (DDR4-2666) 3.9s at +85C < TC +95C - 2400Mbps (DDR4-2400) Fine granularity refresh is supported - 2133Mbps (DDR4-2133) Adjustable internal generation VREFDQ - 1866Mbps (DDR4-1866) Pseudo Open Drain (POD) interface for data input/output - 1600Mbps (DDR4-1600) Driver strength selected by MRS Package The high-speed data transfer by the 8 bits pre-fetch - 78-ball FBGA (A3F4GH20ABF, A3F4GH30ABF) Temperature Controlled Refresh (TCR) mode is - 96-ball FBGA (A3F4GH40ABF) supported - Lead-free Low Power Auto Self Refresh (LPASR) mode is 16 or 8 internal banks supported 4 groups of 4 banks each (x4 and x8) Self refresh abort is supported 2 groups of 4 banks each (x16) Programmable preamble is supported Differential clock inputs operation Write leveling is supported (CK t and CK c) Command/Address latency (CAL) is supported Bi-directional differential data strobe Multipurpose register READ and WRITE capability (DQS t and DQS c) Command Address Parity (CA Parity) for Termination Data Strobe is supported (x8 only) command address signal error detect and inform it (TDQS t and TDQS c) to controller Asynchronous reset is supported Write Cyclic Redundancy Code (CRC) for DQ error (RESET n) detect and inform it to controller during high-speed ZQ calibration for Output driver by compare to operation external reference resistance Data Bus Inversion (DBI) for Improve the power (RZQ 240 ohm 1%) consumption and signalintegrity of the memory Nominal, park and dynamic On-die Termination interface (ODT) Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK Per DRAM Addressability (PDA) for each DRAM transitions can be set a different moderegister value Commands entered on each positive CK edge individually and has individual adjustment CAS Latency (CL): 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, Gear down mode (1/2 and 1/4 rate) is supported 19, 20, 21, 22 and 23 supported PPR and sPPR is supported Additive Latency (AL) 0, CL-1, and CL-2 supported Connectivity test (x16 only) Burst Length (BL): 8 and 4 with on the fly supported Maximum power down mode for the lowest power CAS Write Latency (CWL): 9, 10, 11, 12, 14, 16 and consumption with no internal refresh activity 18 supported JEDEC JESD-79-4 compliant Rev. 02 Oct 15, 2020 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 1 2020 Zentel Japan Corporation. All rights reserved. Doc. No. DSA3F4GH2340ABFF.02 A3F4GH20ABF/A3F4GH30ABF/A3F4GH40ABF 4Gb DDR4 SDRAM CONTENTS Specifications.............................................................................................................................1 Features ................................................................................................................................... 1 1. Ordering Information .............................................................................................................3 2. Part Number ........................................................................................................................ 3 3. Pin Configurations ............................................................................................................... 4 4. Input/Output Functional Description ................................................................................... 7 5. Electrical Conditions .............................................................................................................9 5.1 Absolute Maximum Ratings ........................................................................................9 5.2 Operating Temperature Condition ...............................................................................9 5.3 Recommended DC Operating Conditions ................................................................... 9 5.4 IDD and IDDQ Specification Parameters and Test conditions .................................... 10 6. Electrical Specifications ....................................................................................................... 26 6.1 IDD Specifications ....................................................................................................26 6.2 Input/Output Capacitance .........................................................................................28 6.3 Standard Speed Bins ................................................................................................31 6.4 Electrical Characteristics & AC Timing ................................................................... 37 7. DDR4 Function Matrix ........................................................................................................ 49 8. Package Drawing ............................................................................................................... 50 8.1 78-ball FBGA ............................................................................................................50 8.2 96-ball FBGA ............................................................................................................51 Rev. 02 Oct 15, 2020 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2 2020 Zentel Japan Corporation. All rights reserved.