Doc. No. DSA3T1GF340CBFLF.04 A3T1GF30CBF/A3T1GF40CBF 1Gb DDR3L SDRAM 1Gb DDR3L (1.35V) SDRAM Specification Specifications Features Density: 1G bits The high-speed data transfer is realized by the 8 bits Organization prefetch pipelined architecture o 8 banks x 16M words x 8 bits o 8 banks x 8M words x 16 bits Double data-rate architecture: two data transfers per clock cycle Package o 78-ball FBGA Bi-directional differential data strobe (DQS and /DQS) o 96-ball FBGA is transmitted/received with data for capturing data o Lead-free(RoHS compliant) and Halogen-free at the receiver Power supply: DQS is edge-aligned with data for READs center o VDD, VDDQ =1.35V (1.283 to 1.45V) aligned with data for WRITEs o Backward compatible DDR3 (1.5V) operation Differential clock inputs (CK and /CK) Data Rate: 1333Mbps/1600Mbps/1866Mbps (max.) DLL aligns DQ and DQS transitions with CK transitions 1KB page size (x8) Commands entered on each positive CK edge data o Row address: AX0 to AX13 and data mask referenced to both edges of DQS o Column address: AY0 to AY9 Data mask (DM) for write data 2KB page size (x16) Posted CAS by programmable additive latency for o Row address: AX0 to AX13 better command and data bus efficiency o Column address: AY0 to AY9 On-Die Termination (ODT) for better signal quality Eight internal banks for concurrent operation o Synchronous ODT Burst lengths(BL): 8 and 4 with Burst Chop(BC) o Dynamic ODT Burst type(BT) o Asynchronous ODT o Sequential (8, 4 with BC) Multi Purpose Register (MPR) for pre-defined pattern o Interleave (8, 4 with BC) read out CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13 ZQ calibration for DQ drive and ODT CAS Write Latency (CWL): 5, 6, 7, 8, 9 Programmable Partial Array Self-Refresh (PASR) Precharge: auto precharge option for each burst RESET pin for Power-up sequence and reset function access SRT(Self Refresh Temperature) range: Driver strength: RZQ/7, RZQ/6 (RZQ = 240) o Normal/Extended Refresh: auto-refresh, self-refresh Auto Self-Refresh (ASR) Average refresh period Programmable output driver impedance control o 7.8us at TC +85 JEDEC compliant DDR3 o 3.9us at TC > +85 Operating temperature range o TC = 0C to +95C (Commercial grade) o TC = -40C to +95C (Industrial grade) o TC = -40C to +105C (Automotive grade) Key Timing Parameters Speed Grade Data Rate(Mbps) CL nRCD nRP 1, 2 -HPL 1866 13 13 13 1 -GML 1600 11 11 11 -DKL 1333 9 9 9 Notes: 1. Backward compatible to 1333, CL-nRCD-nRP = 9-9-9 2. Backward compatible to 1600, CL-nRCD-nRP = 11-11-11 Rev. 04 Oct. 14, 2020 1 of 38 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved. Doc. No. DSA3T1GF340CBFLF.04 A3T1GF30CBF/A3T1GF40CBF 1Gb DDR3L SDRAM Table of Contents 1Gb DDR3L (1.35V) SDRAM Specification .......................................................................................................................... 1 1. Ordering Information ............................................................................................................................................ 3 2. Package Ball Assignment ....................................................................................................................................... 4 3. Package outline drawing ....................................................................................................................................... 5 4. Electrical Specifications ......................................................................................................................................... 7 5. Block Diagram ......................................................................................................................................................19 6. Pin Function .........................................................................................................................................................20 7. Command Operation ............................................................................................................................................22 8. Functional Description..........................................................................................................................................26 Rev. 04 Oct. 14, 2020 2 of 38 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved.