Doc. No. DSA3T1GF340CBFF.04 A3T1GF30CBF/A3T1GF40CBF 1Gb DDR3 SDRAM 1Gb DDR3 SDRAM Specification Specifications Features Density: 1G bits The high-speed data transfer is realized by the 8 Organization bits prefetch pipelined architecture o 8 banks x 16M words x 8 bits Double data-rate architecture: two data transfers o 8 banks x 8M words x 16 bits per clock cycle Package Bi-directional differential data strobe (DQS and o 78-ball FBGA /DQS) is transmitted/received with data for o 96-ball FBGA capturing data at the receiver o Lead-free(RoHS compliant) and Halogen-free DQS is edge-aligned with data for READs center Power supply: aligned with data for WRITEs o VDD, VDDQ =1.5V (1.425 to 1.575V) Differential clock inputs (CK and /CK) Data Rate: 1333Mbps/1600Mbps/1866Mbps (max.) DLL aligns DQ and DQS transitions with CK 1KB page size (x8) transitions o Row address: AX0 to AX13 Commands entered on each positive CK edge data o Column address: AY0 to AY9 and data mask referenced to both edges of DQS 2KB page size (x16) Data mask (DM) for write data o Row address: AX0 to AX12 Posted CAS by programmable additive latency for o Column address: AY0 to AY9 better command and data bus efficiency Eight internal banks for concurrent operation On-Die Termination (ODT) for better signal quality Burst lengths(BL): 8 and 4 with Burst Chop(BC) o Synchronous ODT Burst type(BT) o Dynamic ODT o Sequential (8, 4 with BC) o Asynchronous ODT o Interleave (8, 4 with BC) Multi Purpose Register (MPR) for pre-defined CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13 pattern read out CAS Write Latency (CWL): 5, 6, 7, 8, 9 ZQ calibration for DQ drive and ODT Precharge: auto precharge option for each burst Programmable Partial Array Self-Refresh (PASR) access RESET pin for Power-up sequence and reset Driver strength: RZQ/7, RZQ/6 (RZQ = 240) function Refresh: auto-refresh, self-refresh SRT(Self Refresh Temperature) range: Average refresh period o Normal/Extended o 7.8us at TC +85 Auto Self-Refresh (ASR) o 3.9us at TC > +85 Programmable output driver impedance control Operating temperature range JEDEC compliant DDR3 o TC = 0C to +95C (Commercial grade) o TC = -40C to +95C (Industrial grade) o TC = -40C to +105C (Automotive grade) Key Timing Parameters Speed Grade Data Rate(Mbps) CL nRCD nRP 1, 2 -HP 1866 13 13 13 1 -GM 1600 11 11 11 -DK 1333 9 9 9 Notes: 1. Backward compatible to 1333, CL-nRCD-nRP = 9-9-9 2. Backward compatible to 1600, CL-nRCD-nRP = 11-11-11 Rev. 04 Oct. 14, 2020 1 of 36 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved. Doc. No. DSA3T1GF340CBFF.04 A3T1GF30CBF/A3T1GF40CBF 1Gb DDR3 SDRAM Table of Contents 1Gb DDR3 SDRAM Specification ....................................................................................................................... 1 1. Ordering Information ............................................................................................................................ 3 2. Package Ball Assignment ....................................................................................................................... 4 3. Package outline drawing........................................................................................................................ 5 4. Electrical Specifications ......................................................................................................................... 7 5. Block Diagram ..................................................................................................................................... 17 6. Pin Function ........................................................................................................................................ 18 7. Command Operation ........................................................................................................................... 20 8. Functional Description ......................................................................................................................... 24 Rev. 04 Oct. 14, 2020 2 of 36 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved.