Doc. No. DSA3T4GF340BBFF.05 A3T4GF30BBF/A3T4GF40BBF 4Gb DDR3/DDR3L SDRAM 4Gb DDR3/DDR3L SDRAM Specification Specifications Features Density: 4G bits The high-speed data transfer is realized by the 8 Organization bits prefetch pipelined architecture o 8 banks x 64M words x 8 bits Double data-rate architecture: two data transfers o 8 banks x 32M words x 16 bits per clock cycle Package Bi-directional differential data strobe (DQS and o 78-ball FBGA /DQS) is transmitted/received with data for o 96-ball FBGA capturing data at the receiver Power supply: DQS is edge-aligned with data for READs center -HP aligned with data for WRITEs o VDD, VDDQ = 1.35 V (1.283 to 1.45 V) Differential clock inputs (CK and /CK) o Backward compatible with DDR3 operation DLL aligns DQ and DQS transitions with CK VDD, VDDQ = 1.5 V (1.425 to 1.575 V) transitions -JR Commands entered on each positive CK edge data o VDD, VDDQ = 1.5 V (1.425 to 1.575 V) and data mask referenced to both edges of DQS -JRL Data mask (DM) for write data o VDD, VDDQ = 1.35 V (1.283 to 1.45 V) Posted CAS by programmable additive latency for Data Rate: 1866 Mbps/2133 Mbps (max.) better command and data bus efficiency 1KB page size (x8) On-Die Termination (ODT) for better signal quality o Row address: AX0 to AX15 o Synchronous ODT o Column address: AY0 to AY9 o Dynamic ODT 2KB page size (x16) o Asynchronous ODT o Row address: AX0 to AX14 Multi Purpose Register (MPR) for pre-defined o Column address: AY0 to AY9 pattern read out Eight internal banks for concurrent operation ZQ calibration for DQ drive and ODT Burst lengths(BL): 8 and 4 with Burst Chop(BC) Programmable Partial Array Self-Refresh (PASR) Burst type(BT) RESET pin for Power-up sequence and reset o Sequential (8, 4 with BC) function o Interleave (8, 4 with BC) SRT(Self Refresh Temperature) range: CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13, 14 o Normal/Extended CAS Write Latency (CWL): 5, 6, 7, 8, 9, 10 Auto Self-Refresh (ASR) Precharge: auto precharge option for each burst Programmable output driver impedance control access JEDEC compliant DDR3/DDR3L Driver strength: RZQ/7, RZQ/6 (RZQ = 240 ) Row-Hammer-Free (RH-Free): detection/blocking Refresh: auto-refresh, self-refresh circuit inside Average refresh period o 7.8 us at TC +85 o 3.9 us at TC > +85 Operating temperature range o TC = 0C to +95C (Commercial grade) o TC = -40C to +95C (Industrial grade) o TC = -40C to +105C (Automotive grade) Key Timing Parameters Speed Grade Data Rate(Mbps) CL nRCD nRP 1, 2, 3 -JR 2133 14 14 14 1, 2 -HP 1866 13 13 13 Notes: 1. Backward compatible to 1333, CL-nRCD-nRP = 9-9-9 2. Backward compatible to 1600, CL-nRCD-nRP = 11-11-11 3. Backward compatible to 1866, CL-nRCD-nRP = 13-13-13 Rev. 05 Oct. 14, 2020 1 of 49 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved. Doc. No. DSA3T4GF340BBFF.05 A3T4GF30BBF/A3T4GF40BBF 4Gb DDR3/DDR3L SDRAM Table of Contents 4Gb DDR3 SDRAM Specification ................................................................................................................. 1 1. Ordering Information ....................................................................................................................... 3 2. Package Ball Assignment .................................................................................................................. 4 3. Package outline drawing .................................................................................................................. 5 4. Electrical Specifications .................................................................................................................... 7 5. Block Diagram................................................................................................................................ 30 6. Pin Function................................................................................................................................... 31 7. Command Operation ..................................................................................................................... 33 8. Functional Description ................................................................................................................... 37 Rev. 05 Oct. 14, 2020 2 of 49 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved.