Doc. No. DSA3T8GF343BBFLF.04 A3T8GF33BBF/A3T8GF43BBF 8Gb 1Rank DDR3L SDRAM 8Gb 1Rank DDR3L Specification Specifications Features Density: 8G bits The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture Organization o 1Rank x 8 banks x 128M words x 8 bits Double data-rate architecture: two data transfers o 1Rank x 8 banks x 64M words x 16 bits per clock cycle Package Bi-directional differential data strobe (DQS and o 78-ball FBGA /DQS) is transmitted/received with data for o 96-ball FBGA capturing data at the receiver o Lead-free(RoHS compliant) and Halogen-free DQS is edge-aligned with data for READs center Power supply: aligned with data for WRITEs o VDD, VDDQ =1.35V (1.283 to 1.45V) Differential clock inputs (CK and /CK) Data Rate: 1600Mbps/1866Mbps (max.) DLL aligns DQ and DQS transitions with CK 2KB page size transitions o Row address: AX0 to AX15 (x8)(x16) Commands entered on each positive CK edge data o Column address: AY0 to AY9 A11 (x8) and data mask referenced to both edges of DQS o Column address: AY0 to AY9 (x16) Data mask (DM) for write data Eight internal banks for concurrent operation Posted CAS by programmable additive latency for Burst lengths(BL): 8 and 4 with Burst Chop(BC) better command and data bus efficiency Burst type(BT) On-Die Termination (ODT) for better signal quality o Sequential (8, 4 with BC) o Synchronous ODT o Interleave (8, 4 with BC) o Dynamic ODT CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13 o Asynchronous ODT CAS Write Latency (CWL): 5, 6, 7, 8, 9 Multi Purpose Register (MPR) for pre-defined Precharge: auto precharge option for each burst pattern read out access ZQ calibration for DQ drive and ODT Driver strength: RZQ/7, RZQ/6 (RZQ =240) Programmable Partial Array Self-Refresh (PASR) Refresh: auto-refresh, self-refresh RESET pin for Power-up sequence and reset function Average refresh period o 7.8us at TC +85 SRT(Self Refresh Temperature) range: o 3.9us at TC > +85 o Normal/Extended Operating temperature range Auto Self-Refresh (ASR) o TC = 0C to +95C (Commercial grade) Programmable output driver impedance control o TC = -40C to +95C (Industrial grade) JEDEC compliant DDR3 Row-Hammer-Free (RH-Free): detection/blocking circuit inside Key Timing Parameters nRCD Speed Grade Data Rate(Mbps) CL nRP -HPL 1866 13 13 13 -GML 1600 11 11 11 Rev. 04 Oct. 14, 2020 1 of 35 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved. Doc. No. DSA3T8GF343BBFLF.04 A3T8GF33BBF/A3T8GF43BBF 8Gb 1Rank DDR3L SDRAM Table of Contents 8Gb 1Rank DDR3L Specification ........................................................................................................................................ 1 1. Ordering Information ............................................................................................................................................ 3 2. Package Ball Assignment ....................................................................................................................................... 4 3. Package outline drawing ....................................................................................................................................... 5 4. Electrical Specifications ......................................................................................................................................... 7 5. Pin Function .........................................................................................................................................................17 6. Command Operation ............................................................................................................................................19 7. Functional Description..........................................................................................................................................23 Rev. 04 Oct. 14, 2020 2 of 35 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved.