A3V28S40JTP-60I Zentel

Doc. No. DSA3V28S40JTPF.02 A3V28S40JTP 128Mb SDR SDRAM 128Mb Synchronous DRAM Specification A3V28S40JTP Zentel Japan Corp. Rev. 02 Oct. 13, 2020 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved. Page 1/41 Doc. No. DSA3V28S40JTPF.02 A3V28S40JTP 128Mb SDR SDRAM General Description A3V28S40JTP is organized as 4-bank x 2,097,154-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. A3V28S40JTP achieve very high speed data rates up to 166 MHz, and are suitable for main memories or graphic memories in computer systems. Features Single 3.3V 0.3V power supply Maximum clock frequency: - 60: 166 MHz<3-3-3> (Backward compatible to 143 MHz<3-3-3> and 133 MHz<3-3-3>) Operating temperature: - Commercial: 0 to 70C - Industrial: -40 to 85C Fully synchronous operation referenced to clock rising edge 4-bank operation controlled by BA0, BA1 (Bank Address) CAS latency- 2/3 (programmable) Burst length- 1/2/4/8/FP (programmable) Burst type- Sequential and interleave burst (programmable) Byte Control by LDQM and UDQM Random column access Auto precharge / All bank precharge controlled by A10 Support concurrent auto-precharge Auto and self refresh 4096 refresh cycles / 64ms LVTTL Interface Package: - 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch Rev. 02 Oct. 13, 2020 Zentel Japan Corporation reserves the right to change products and/or specifications without notice. 2020 Zentel Japan Corporation. All rights reserved. Page 2/41