96D3-8G1600NN-APL Advantech

Apacer Technology Inc. CUSTOMER: APPROVAL SHEET APPROVED NO. : 90004-T0021 ISSUE DATE : July-12-2012 MODULE PART NO. : 78.C1GET.ATF0C PCB PART NO. : 48.18213.09F0C IC Brand : Micro DESCRIPTION : DDR3 DIMM 12800-11 512x8 8GB MC VLP G CUSTOMER APPROVAL : Apacer Technology Inc. Authorized by : Steven Wang Apacer Memory Product Specification 8GB Unbuffered VLP DDR3 SDRAM DIMM with SPD Ordering Information Component Number of Part Number Bandwidth Speed Grade Max Frequency CAS Latency Density Organization Composition Rank 78.C1GET.ATF0C 12.8GB/sec 1600Mbps 800MHz CL11 512Mx8*16EA 8GB 1024Mx64 2 Specifications Features On Dimm Thermal Sensor: No Double-data-rate architecture two data transfers per clock cycle Density: 8GB The high-speed data transfer is realized by the 8 bits Organization prefetch pipelined architecture 1024M words 64 bits, 2 ranks Bi-directional differential data strobe (DQS and /DQS) Mounting 16 pieces of 4G bits DDR3 SDRAM sealed is transmitted/received with data for capturing data at in FBGA the receiver Package: 240-pin socket type dual in line memory DQS is edge-aligned with data for READs center- module (DIMM) aligned with data for WRITEs PCB height: 18.75mm Differential clock inputs (CK and /CK) Lead pitch: 1.0mm (pin) DLL aligns DQ and DQS transitions with CK Lead-free (RoHS compliant) transitions Power supply: VDD = 1.5V 0.075V Commands entered on each positive CK edge data and data mask referenced to both edges of DQS Eight internal banks for concurrent operation (components) Data mask (DM) for write data Interface: SSTL 15 Posted /CAS by programmable additive latency for Burst lengths (BL): 8 and 4 with Burst Chop (BC) better command and data bus efficiency /CAS Latency (CL): 6, 7, 8, 9, 10, 11 On-Die-Termination (ODT) for better signal quality Synchronous ODT /CAS write latency (CWL): 5, 6, 7 Dynamic ODT Precharge: auto precharge option for each burst access Asynchronous ODT Refresh: auto-refresh, self-refresh Multi Purpose Register (MPR) for temperature read Refresh cycles out Average refresh period ZQ calibration for DQ drive and ODT 7.8 s at 0C TC +85C Programmable Partial Array Self-Refresh (PASR) 3.9 s at +85C < TC +95C /RESET pin for Power-up sequence and reset Operating case temperature range function TC = 0C to +95C SRT range: Normal/extended Auto/manual self-refresh Programmable Output driver impedance control