Apacer Technology Inc. CUSTOMER: APPROVAL SHEET APPROVED NO. : 90004-T0014 ISSUE DATE : May-17-2012 MODULE PART NO. : 78.B2GCJ.AF10C PCB PART NO. : 48.18220.091 IC Brand : Hynix DESCRIPTION : DDR3 SODIMM 12800-11 256x8 4GB HYN G CUSTOMER APPROVAL : Apacer Technology Inc. Authorized by : Steven Wang Apacer Memory Product Specification 4GB DDR3 SDRAM SODIMM with SPD Ordering Information Component Number of Part Number Bandwidth Speed Grade Max Frequency CAS Latency Density Organization Composition Rank 1600Mbps 800MHz CL11 78.B2GCJ.AF10C 12.8GB/sec 4GB 512Mx64 256Mx8*16EA 2 Specifications Features On Dimm Thermal Sensor: No Double-data-rate architecture two data transfers per clock cycle Density: 4GB The high-speed data transfer is realized by the 8 bits Organization prefetch pipelined architecture 512M words 64 bits, 2 ranks Bi-directional differential data strobe (DQS and /DQS) Mounting 16 pieces of 2G bits DDR3 SDRAM sealed is transmitted/received with data for capturing data at in FBGA the receiver Package: 204-pin socket type small outline dual in DQS is edge-aligned with data for READs center- line memory module (SO-DIMM) aligned with data for WRITEs PCB height: 30.0mm Differential clock inputs (CK and /CK) Lead pitch: 0.6mm (pin) DLL aligns DQ and DQS transitions with CK Lead-free (RoHS compliant) transitions Power supply: VDD = 1.5V 0.075V Commands entered on each positive CK edge data and data mask referenced to both edges of DQS Eight internal banks for concurrent operation (components) Data mask (DM) for write data Interface: SSTL 15 Posted /CAS by programmable additive latency for Burst lengths (BL): 8 and 4 with Burst Chop (BC) better command and data bus efficiency /CAS Latency (CL): 6, 7, 8, 9, 10, 11 On-Die-Termination (ODT) for better signal quality Synchronous ODT /CAS write latency (CWL): 5, 6, 7, 8 Dynamic ODT Precharge: auto precharge option for each burst access Asynchronous ODT Refresh: auto-refresh, self-refresh Multi Purpose Register (MPR) for temperature read Refresh cycles out Average refresh period ZQ calibration for DQ drive and ODT 7.8 s at 0C TC +85C Programmable Partial Array Self-Refresh (PASR) 3.9 s at +85C < TC +95C /RESET pin for Power-up sequence and reset Operating case temperature range function TC = 0C to +95C SRT range: Normal/extended Auto/manual self-refresh Programmable Output driver impedance control