288Pin DDR4 2133 ECC UDIMM 8GB Based on 512Mx8 AQD-D4U8GE21-SG Advantech AQD-D4U8GE21-SG Datasheet Rev. 1.0 2015-03-16 1 288Pin DDR4 2133 ECC UDIMM 8GB Based on 512Mx8 AQD-D4U8GE21-SG Description Pin Identification Symbol Function DDR4 ECC U-DIMMs are high-speed and low power A0A14 SDRAM address bus memory modules that use 512Mx8bits DDR4 SDRAM in BA0, BA1 SDRAM bank select FBGA package and a 4K-bit serial EEPROM on a 288-pin BG0, BG1 SDRAM bank group select RAS n SDRAM row address strobe printed circuit board. DDR4 ECC U-DIMMs are dual CAS n SDRAM column address strobe In-Line memory modules and are intended for mounting WE n SDRAM write enable into 288-pin edge connector sockets. CS0 n, CS1 n DIMM Rank Select Lines The synchronous design allows precise cycle control with CKE0, CKE1 SDRAM clock enable lines SDRAM on-die termination control the use of system clock. Data I/O transactions are ODT0, ODT1 lines possible on both edges of DQS. The large range of ACT n SDRAM activate operation frequencies and programmable latencies allow DQ0DQ63 DIMM memory data bus the same device to be useful for a variety of high CB0CB7 DIMM ECC check bits Input data mask and data bus bandwidth and high performance memory system DM n/DBI n/ inversion applications. SDRAM data strobes DQS0 tDQS8 t (positive line of differential pair) Features SDRAM data strobes DQS0 cDQS8 c RoHS compliant (negative line of differential pair) JEDEC standard 1.2V 0.06V power supply SDRAM clocks CK0 t, CK1 t (positive line of differential pair) VDDQ=1.2V 0.06V SDRAM clocks Clock Freq: 1067MHZ for 2133Mb/s/Pin. CK0 c, CK1 c (negative line of differential pair) Programmable CAS Latency: 10,11,12,13,14,15,16 PARITY SDRAM parity input VDD SDRAM I/O and core power supply Programmable Additive Latency (Posted /CAS): SDRAM command/address 0,CL-2 or CL-1 clock VREFCA reference supply Programmable /CAS Write Latency (CWL) VSS Power supply return (ground) = 11, 14(DDR4-2133) Serial SPD EEPROM positive VDDSPD power supply 8 bit pre-fetch 2 SCL I C serial bus clock for EEPROM Burst Length: 4, 8 2 I C serial bus data line for SDA Bi-directional Differential Data-Strobe EEPROM 2 On Die Termination with ODT pin I C slave address select for SA0SA2 EEPROM Serial presence detect with EEPROM ALERT n SDRAM ALERT n On DIMM Thermal Sensor VPP SDRAM Supply Asynchronous reset RESET n Set DRAMs to a Known State SPD signals a thermal event has EVENT n occurred VTT SDRAM I/O termination supply RFU Reserved for future use NC No Connection 2