260 Pin DDR4 1.2V 2400 SO-DIMM 16GB Based on 1Gx8 AQD-SD4U16N24-SE Advantech AQD-SD4U16N24-SE Datasheet Rev. 1.0 2017-01-05 Advantech 11 260 Pin DDR4 1.2V 2400 SO-DIMM 16GB Based on 1Gx8 AQD-SD4U16N24-SE Description Pin Identification DDR4 1.2V SO-DIMM is high-speed, low power memory Symbol Function module that use 1Gx8bits DDR4 SDRAM in FBGA A0A16 Register address input package and a 4096 bits serial EEPROM on a 260-pin BA0, BA1 Register bank select input printed circuit board. DDR4 1.2V SO-DIMM is a Dual BG0, BG1 Register bank group select input In-Line Memory Module and is intended for mounting into 260-pin edge connector sockets. RAS n1 Register row address strobe input Synchronous design allows precise cycle control with the CAS n2 Register column address strobe input use of system clock. Data I/O transactions are possible WE n3 Register write enable input on both edges of DQS. Range of operation frequencies, programmable latencies allow the same device to be CS0 n, CS1 n, DIMM Rank Select Lines input useful for a variety of high bandwidth, high performance CKE0, CKE1 Register clock enable lines input memory system applications. Register on-die termination control lines ODT0, ODT1 input Features ACT n Register input for activate input RoHS compliant products JEDEC standard 1.2V (1.14V to 1.26V) Power supply DQ0DQ63 DIMM memory data bus VDDQ=1.2V (1.14V to 1.26V) CB0CB7 DIMM ECC check bits Clock Freq: 1200MHZ for 2400Mb/s/Pin DQS0 t Data Buffer data strobes (positive line 16 Banks (4 Bank Groups) DQS17 t of differential pair) Programmable CAS Latency: 10, 11, 12, 13, 14,15,16, DQS0 c Data Buffer data strobes (negative line 17,18 DQS17 c of differential pair) Programmable Additive Latency (Posted /CAS): Register clock input (positive line of 0,CL-2 or CL-1 clock CK0 t, CK1 t differential pair) Programmable /CAS Write Latency (CWL) = 12,16 (DDR4-2400) Register clocks input (negative line of CK0 c, CK1 c 8 bit pre-fetch differential pair) Burst Length: 4, 8 I2C serial bus clock for SPD/TS and Bi-directional Differential Data-Strobe SCL register On Die Termination with ODT pin I2C serial bus data line for SPD/TS and Serial presence detect with EEPROM SDA Asynchronous reset register PCB: 30 gold finger I2C slave address select for SPD/TS SA0SA2 and register PARITY Register parity input Advantech 22