Standard Products ACT 7000SC 64-Bit Superscaler Microprocessor www.aeroflex.com/Avionics October 9, 2009 FEATURES Embedded application enhancements Full militarized QED RM7000 microprocessor Specialized DSP integer Multiply-Accumulate Dual Issue symmetric superscalar instruction, (MAD/MADU) and three-operand microprocessor with instruction prefetch multiply instruction (MUL/U) optimized for system level price/performance Per line cache locking in primaries and secondary 150, 200, 210, 225 MHz operating frequency Bypass secondary cache option Consult Factory for latest speeds I&D Test/Break-point (Watch) registers for MIPS IV Superset Instruction Set Architecture emulation & debug Performance counter for system and software High performance interface (RM52xx tuning & debug compatible) Ten fully prioritized vectored interrupts - 600 MB per second peak throughput 6 external, 2 internal, 2 software 75 MHz max. freq., multiplexed address/data Fast Hit-Writeback-Invalidate and Hit-Invalidate Supports 1/2 clock multipliers (2, 2.5, 3, 3.5, 4, cache operations for efficient cache management 4.5, 5, 6, 7, 8, 9) High-performance floating point unit - IEEE 1149.1 JTAG (TAP) boundary scan 600 M FLOPS maximum Integrated primary and secondary caches - all Single cycle repeat rate for common are 4-way set associative with 32 byte line size single-precision operations and some 16KB instruction double-precision operations 16KB data: non-blocking and write-back or Single cycle repeat rate for single-precision write-through combined multiply- add operations 256KB on-chip secondary: unified, non-blocking, Two cycle repeat rate for double-precision block writeback multiply and double-precision combined MIPS IV instruction set multiply-add operations Data PREFETCH instruction allows the Fully static CMOS design with dynamic power processor to overlap cache miss latency and down logic instruction execution Standby reduced power mode with WAIT Floating point combined multiply-add instruction instruction increases performance in signal processing and 4 watts typical 2.5V Int., 3.3V I/O, 200MHz graphics applications 208-lead CQFP, cavity-up package (F17) Conditional moves reduce branch frequency Index address modes (register + register) 208-lead CQFP, inverted footprint (F24), with Embedded supply de-coupling capacitors and the same pin rotation as the commercial QED additional PLL filter components RM5261 Integrated memory management unit (ACT52xx compatible) Fully associative joint TLB (shared by I and D translations) 48 dual entries map 96 pages 4 entry DTLB and 4 entry ITLB Variable page size (4KB to 16MB in 4x increments) SCD7000 Rev DOn - Chip 256K Byte Secondary Cache, 4 - Way Set Associative Secondary Tags Secondary Tags Secondary Tags Secondary Tags Set A Set B Set C Set D ITag Primary Data Cache DTag Primary Instruction Cache 4 - Way Set Associative 4 - Way Set Associative DTLB ITLB A/D Bus Pad Bus Store Buffer Pad Buffer Prefetch Buffer Write Buffer Address Buffer Instruction Dispatch Unit Read Buffer F Pipe Register M Pipe Register F-Pipe Bus M-Pipe Bus D Bus Floating-Point Load Aligner Joint TLB DVA Load / Align Integer Register File Coprocessor 0 Floating-Point M Pipe F Pipe Register File Adder Adder System / Memory Packer / Unpacker IVA Control StAin/Sh Shifter Comparator Logicals Logicals PC Incrementer Floating-Point FA Bus MultAdd, Add, Sub, Branch PC Adder Cvt, Div, Sqrt DTLB Virtuals ITLB Virtuals PLL/Clocks Int Mult. Div. Madd Multiplier Array Program Counter Block Diagram SCD7000 Rev D 10/9/09 Aeroflex Plainview 2 Floating - Point Control Integer Control