ADC102S051 www.ti.com SNAS262H NOVEMBER 2004REVISED MARCH 2013 ADC102S051 2 Channel, 200 ksps to 500 ksps, 10-Bit A/D Converter Check for Samples: ADC102S051 1FEATURES DESCRIPTION The ADC102S051 is a low-power, two-channel 2 Specified Over a Range of Sample Rates. CMOS 10-bit analog-to-digital converter with a high- Two Input Channels speed serial interface. Unlike the conventional Variable Power Management practice of specifying performance at a single sample rate only, the ADC102S051 is fully specified over a Single Power Supply with 2.7V - 5.25V Range sample rate range of 200 ksps to 500 ksps. The converter is based on a successive-approximation KEY SPECIFICATIONS register architecture with an internal track-and-hold DNL: 0.13 LSB (typ) circuit. It can be configured to accept one or two input signals at inputs IN1 and IN2. INL: + 0.20/0.1 LSB (typ) SNR: 61.8 dB (typ) The output serial data is straight binary, and is compatible with several standards, such as SPI, Power Consumption: QSPI, MICROWIRE, and many common DSP serial 3V Supply: 2.7 mW (typ) interfaces. 5V Supply: 8.6 mW (typ) The ADC102S051 operates with a single supply that can range from +2.7V to +5.25V. Normal power APPLICATIONS consumption using a +3V or +5V supply is 2.7 mW Portable Systems and 8.6 mW, respectively. The power-down feature reduces the power consumption to just 0.12 W using Remote Data Acquisition a +3V supply, or 0.47 W using a +5V supply. Instrumentation and Control Systems The ADC102S051 is packaged in an 8-lead VSSOP package. Operation over the industrial temperature range of 40C to +85C is ensured. (1) Table 1. Pin-Compatible Alternatives by Resolution and Speed Resolution Specified for Sample Rates of: 50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps 12-bit ADC122S021 ADC122S051 ADC122S101 10-bit ADC102S021 ADC102S051 ADC102S101 8-bit ADC082S021 ADC082S051 ADC082S101 (1) All devices are fully pin and function compatible. Connection Diagram CS 1 8 SCLK 7 V 2 DOUT A ADC102S051 GND 3 6 DIN IN2 4 5 IN1 Figure 1. VSSOP Package See Package Number DGK0008A 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 20042013, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.ADC102S051 SNAS262H NOVEMBER 2004REVISED MARCH 2013 www.ti.com Block Diagram 10-BIT V IN1 A SUCCESSIVE MUX T/H APPROXIMATION IN2 ADC GND GND SCLK CS CONTROL LOGIC DIN DOUT Pin Descriptions and Equivalent Circuits Pin No. Pin Name Description ANALOG I/O 5,4 IN1 and IN2 Analog inputs. These signals can range from 0V to V . A DIGITAL I/O 8 SCLK Digital clock input. This clock directly controls the conversion and readout processes. Digital data output. The output samples are clocked out of this pin on falling edges of the 7 DOUT SCLK pin. Digital data input. The ADC102S051 s Control Register is loaded through this pin on rising 6 DIN edges of the SCLK pin. Chip select. On the falling edge of CS, a conversion process begins. Conversions continue 1 CS as long as CS is held low. POWER SUPPLY Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and 2 V bypassed to GND with a 1 F capacitor and a 0.1 F monolithic capacitor located within 1 A cm of the power pin. 3 GND The ground return for the die. 2 Submit Documentation Feedback Copyright 20042013, Texas Instruments Incorporated Product Folder Links: ADC102S051