MCP33131D/21D/11D-XX 1 Msps/500 kSPS 16/14/12-Bit Differential Input SAR ADC Features Typical Applications Sample Rate (Throughput): High-Precision Data Acquisition - MCP33131D/21D/11D-10: 1 Msps Medical Instruments - MCP33131D/21D/11D-05: 500 kSPS Test Equipment 16/14/12-Bit Resolution with No Missing Codes Electric Vehicle Battery Management Systems No Latency Output Motor Control Applications Wide Operating Voltage Range: Switch-Mode Power Supply Applications - Analog Supply Voltage (AV ): 1.8V DD Battery-Powered Equipment ): - Digital Input/Output Interface Voltage (DV IO 1.7V - 5.5V System Design Supports ): 2.5V - 5.1V - External Reference (V REF The MCP331x1D-XX Evaluation Kit demonstrates the Differential Input Operation performance of the MCP331x1D-XX SAR ADC family - Input Full-Scale Range: -V to +V REF REF devices. The evaluation kit includes: (a) MCP331x1D Ultra Low Current Consumption (typical): Evaluation Board, (b) PIC32MZ EF Curiosity Board for data collection, and (c) SAR ADC Utility PC GUI. - During Input Acquisition (Standby): ~ 0.8 A - During Conversion: Contact Microchip Technology Inc. for the evaluation tools and the PIC32 MCU firmware example codes. MCP33131D/21D/11D-10: ~1.6 mA MCP33131D/21D/11D-05: ~1.4 mA Package Types SPI-Compatible Serial Communication: V 1 10 DV - SCLK Clock Rate: up to 100 MHz REF IO ADC Self-Calibration for Offset, Gain, and MSOP-10 AV 2 9 SDI DD Top View Linearity Errors: A + 3 8 SCLK IN - During Power-Up (automatic) A - 4 7 SDO IN - On-Demand via users command during GND 5 6 CNVST normal operation AEC-Q100 Qualified: V 1 10 DV REF IO - Temperature Grade 1: -40C to +125C TDFN-10 AV 2 9 SDI DD Package Options: MSOP-10 and TDFN-10 Top View A + SCLK 3 8 IN A - 4 7 IN SDO 5 GND 6 CNVST MCP331x1D-XX Device Offering (Note 1): Performance (Typical) Sample Input Range Part Number Resolution Input Type SNR SFDR THD INL DNL Rate (Differential) (dBFS) (dB) (dB) (LSB) (LSB) MCP33131D-10 16-bit 1 Msps Differential 5.1V 91.3 103.5 -99.3 2 0.8 MCP33121D-10 14-bit 1 Msps Differential 5.1V 85.1 103.5 -99.2 0.5 0.25 MCP33111D-10 12-bit 1 Msps Differential 5.1V 73.9 99.3 -96.7 0.12 0.06 MCP33131D-05 16-bit 500 kSPS Differential 5.1V 91.3 103.5 -99.3 2 0.8 MCP33121D-05 14-bit 500 kSPS Differential 5.1V 85.1 103.5 -99.2 0.5 0.25 MCP33111D-05 12-bit 500 kSPS Differential 5.1V 73.9 99.3 -96.7 0.12 0.06 Note 1: SNR, SFDR, and THD are measured with f = 10 kHz, V = -1 dBFS, V = 5.1V. IN IN REF 2018 Microchip Technology Inc. DS20005947B-page 1MCP33131D/MCP33121D/MCP33111D-XX Application Diagram 2.5V to 5.1V 1.8V 1.8V to 5.5V V AV DV REF DD IO 22 A + IN 0V to V REF 1.7 nF SDI MCP331x1D-XX Host Device CNVST 22 SCLK (PIC32MZ) A - IN SDO 0V to V REF GND 1.7 nF During Standby, most of the internal analog circuitry is Description shutdown in order to reduce current consumption. The MCP33131D/MCP33121D/MCP33111D-10 and Typically, the device consumes less than 1 A during MCP33131D/MCP33121D/MCP33111D-05 are Standby. A new conversion is started on the rising edge fully-differential 16, 14, and 12-bit, single-channel of CNVST. When the conversion is complete and the 1Msps and 500kSPS ADC family devices, host lowers CNVST, the output data is presented on respectively, featuring low power consumption and SDO, and the device enters Standby to begin acquiring high performance, using a successive approximation the next input sample. The user can clock out the ADC register (SAR) architecture. output data using the SPI-compatible serial clock during Standby. The device operates with a 2.5V to 5.1V external reference (V ), which supports a wide range of input REF The ADC system clock is generated by the internal full-scale range from -V to +V . The reference REF REF on-chip clock, therefore the conversion is performed voltage setting is independent of the analog supply independent of the SPI serial clock (SCLK). voltage (AV ) and is higher than AV The DD DD. This device can be used for various high-speed and conversion output is available through an easy-to-use high-accuracy analog-to-digital data conversion simple SPI- compatible 3-wire interface. applications, where design simplicity, low power, and The device requires a 1.8V analog supply voltage no output latency are needed. (AV ) and a 1.7V to 5.5V digital I/O interface supply DD The device is AEC-Q100 qualified for automotive appli- voltage (DV ). The wide digital I/O interface supply IO cations and operates over the extended temperature (DV ) range (1.7V5.5V) allows the device to IO range of -40C to +125C. The available package interface with most host devices (Master) available in options are Pb-free small 3 mm x 3 mm TDFN-10 and the current industry such as the PIC32 MSOP-10. microcontrollers, without using external voltage level shifters. When the device is first powered-up, it performs a self-calibration to minimize offset, gain and linearity errors. The device performance stays stable across the specified temperature range. However, when extreme changes in the operating environment, such as in the reference voltage, are made with respect to the initial conditions (e.g. the reference voltage was not fully settled during the initial power-up sequence), the user may send a recalibrate command anytime to initiate another self-calibration to restore optimum performance. When the initial power-up sequence is completed, the device enters a low-current input acquisition mode, where sampling capacitors are connected to the input pins. This mode is called Standby. DS20005947B-page 2 2018 Microchip Technology Inc.