A43L3616A Series 2M x 16 Bit x 4 Banks Synchronous DRAM Preliminary Document Title 2M x 16 Bit x 4 Banks Synchronous DRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue August 7, 2007 Preliminary 0.1 Change clock frequency from 133MHz to 143MHz at 7ns cycle November 14, 2007 time 0.2 February 20, 2008 Add part numbering scheme 0.3 Add A43L4608A part number May 5, 2008 Modify DC spec. 0.4 Add Test Mode description August 13, 2008 0.5 Add automotive temperature grade November 11, 2008 0.6 Remove A43L4608A part number January 7, 2009 Modify DC current spec. 0.7 Add 54 balls CSP (8mm x 8mm) package August 28, 2009 0.8 Modify tRAS(max.) from 100ns to 100s November 8, 2011 PRELIMINARY (November, 2011, Version 0.8) AMIC Technology, Corp. A43L3616A Series 2M x 16 Bit x 4 Banks Synchronous DRAM Preliminary Features JEDEC standard 3.3V 0.3V power supply Industrial operating range: -40 C to +85C for U LVTTL compatible with multiplexed address Automotive temperature operation:-40 C to +85C for -A Burst Read Single-bit Write operation Four banks / Pulse RAS DQM for masking MRS cycle with address key programs Auto & self refresh - CAS Latency (2,3) 64ms refresh period (4K cycle) - Burst Length (1,2,4,8) Available in 54 Balls CSP (8mm X 8mm) and 54-pin - Burst Type (Sequential & Interleave) TSOP(II) packages All inputs are sampled at the positive going edge of the Package is available to lead free (-F series) system clock All Pb-free (Lead-free) products are RoHS compliant General Description The A43L3616A is 134,217,728 bits synchronous high data every clock cycle. Range of operating frequencies, rate Dynamic RAM organized as 4 X 2,097,152 words by 16 programmable latencies allow the same device to be useful bits, abricated with AMICs high performance CMOS for a variety of high bandwidth, high performance memory technology. Synchronous design allows precise cycle control system applications. with the use of system clock. I/O transactions are possible on Pin Configuration 54 Balls CSP (8 mm x 8 mm) Top View 54 Ball (6X9) CSP 1 2 3 7 8 9 A VSS DQ15 VSSQ VDDQ DQ0 VDD B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1 C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 NC VSS VDD LDQM DQ7 F UDQM CLK CKE CAS RAS WE G NC A11 A9 BA0 BA1 CS H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD PRELIMINARY (November, 2011, Version 0.8) 1 AMIC Technology, Corp.