SN74SSQEB32882 www.ti.com SCAS896-PUB JUNE 2010 28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver Check for Samples: SN74SSQEB32882 1 FEATURES Checks Parity on Command and Address (CS-Gated) Data Inputs 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs Configurable Driver Strength CKE Powerdown Mode for Optimized System Uses Internal Feedback Loop Power Consumption APPLICATIONS 1.5V/1.35V/1.25V Phase Lock Loop Clock DDR3 Registered DIMMs up to DDR3-1866 Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four DDR3L Registered DIMMs up to DDR3L-1600 Differential Outputs DDR3U Registered DIMMs up to DDR3U-1333 1.5V/1.35V/1.25V CMOS Inputs Single-, Dual- and Quad-Rank RDIMM DESCRIPTION This JEDEC SSTE32882 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with V of 1.5 V, on DDR3L registered DIMMs with V of 1.35 V and on DD DD DDR3U registered DIMMs with V of 1.25 V. DD All inputs are 1.5 V, 1.35V and 1.25 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn and DxODTn can be driven with a different strength and skew to optimize signal integrity, compensate for different loading and equalize signal travel speed. The SN74SSQEB32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is theQuadCS disable mode. When the QCSEN input pin is pulled low, the component has four chip select inputs DCS 3:0 , and four chip select outputs, QCS 3:0 . This is theQuadCS enable mode. Through the remainder of this specification, DCS n:0 will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled. QxCS n:0 will indicate all of the chip select outputs. The device also supports a mode where a single device can be mounted on the back side of a DIMM. If MIRROR=HIGH, Input Bus Termination (IBT) has to stay enabled for all input signals in this case. The SN74SSQEB32882 operates from a differential clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. This data could be either re-driven to the outputs or it could be used to access device internal control registers. The input bus data integrity is protected by a parity function. All address and command input signals are added up and the last bit of the sum is compared to the parity signal delivered by the system at the input PAR IN one clock cycle later. If they do not match the device pulls the open drain output ERROUT LOW. The control signals (DCKE0, DCKE1, DODT0, DODT1, DCS n:0 ) are not part of this computation. The SN74SSQEB32882 implements different power saving mechanisms to reduce thermal power dissipation and to support system power down states. By disabling unused outputs the power consumption is further reduced. The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk design with low interconnect latency. Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright 2010, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.SN74SSQEB32882 SCAS896-PUB JUNE 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. ORDERING INFORMATION (2) ORDERABLE TOP-SIDE (1) T PACKAGE PART NUMBER MARKING CASE(max) See Table 4 176ZAL Tape and Reel SN74SSQEB32882ZALR EB32882A (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. APPLICATION INFORMATION Vendor Specific SPD Content SPD EEPROM on DDR3 RDIMMs has 3 vendor specific bytes for vendor and revision ID. This information can be sued by the system BIOS. The following table showsthe correct values for SN74SSQEB32882. Table 2. Vendor specific SPD content for SN74SSQEB32882 Byte Value Description 65 0x80 Vendor ID, part 1 66 0x97 Vendor ID, part 2 67 0x33 Revision ID Application Reports For additional Information on SN74SSQEB32882 DDR3 Register please review the following application reports: - DDR3 Register CMR programming - DDR3 RDIMM SPD settings - Yn phase shift on SN74SSQEA32882 - DDR3 Register IBT Measurement 2 Submit Documentation Feedback Copyright 2010, Texas Instruments Incorporated