INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7030
9-bit x 64-word FIFO register;
3-state
December 1990
Product specication
File under Integrated Circuits, IC06Philips Semiconductors Product specication
9-bit x 64-word FIFO register; 3-state 74HC/HCT7030
FEATURES Data outputs (Q to Q )
0 8
Synchronous or asynchronous operation
As there is no weighting of the outputs, any output can be
assigned as the MSB. The size of the FIFO memory can
3-state outputs
be reduced from the 9 64 configuration as described for
Master-reset input to clear control functions
data inputs. In a reduced format, the unused data output
33 MHz (typ.) shift-in, shift-out rates with or without flags
pins must be left open circuit.
Very low power consumption
Master-reset (MR)
Cascadable to 25 MHz (typ.)
When MR is LOW, the control functions within the FIFO
Readily expandable in word and bit dimensions
are cleared, and data content is declared invalid. The
Pinning arranged for easy board layout: input pins
data-in-ready (DIR) flag is set HIGH and the
directly opposite output pins
data-out-ready (DOR) flag is set LOW. The output stage
Output capability: standard
remains in the state of the last word that was shifted out,
or in the random state existing at power-up.
I category: LSI
CC
Status flag outputs (DIR, DOR)
GENERAL DESCRIPTION
Indication of the status of the FIFO is given by two status
The 74HC/HCT7030 are high-speed Si-gate CMOS
flags, data-in-ready (DIR) and data-out-ready (DOR):
devices specified in compliance with JEDEC standard
no. 7A.
DIR = HIGH indicates the input stage is empty and
ready to accept valid data
The 74HC/HCT7030 is an expandable, First-In First-Out
(FIFO) memory organized as 64 words by 9 bits. A 33 MHz
DIR = LOW indicates that the FIFO is full or that a
data-rate makes it ideal for high-speed applications. Even
previous shift-in operation is not complete
at high frequencies, the I dynamic is very low
CC (busy)
(f = 18 MHz; V = 5 V produces a dynamic I of
max CC CC
DOR = HIGH assures valid data is present at the
80 mA). If the device is not continuously operating at f ,
max
outputs Q to Q (does not indicate that new
0 8
then I will decrease proportionally.
CC
data is awaiting transfer into the output stage)
With separate controls for shift-in (SI) and shift-out (SO),
DOR = LOW indicates the output stage is busy or
reading and writing operations are completely
there is no valid data
independent, allowing synchronous and asynchronous
data transfers. Additional controls include a master-reset
Shift-in control (SI)
input (MR) and an output enable input (OE). Flags for
Data is loaded into the input stage on a LOW-to-HIGH
data-in-ready (DIR) and data-out-ready (DOR) indicate the
transition of SI. A HIGH-to-LOW transition triggers an
status of the device.
automatic data transfer process (ripple through). If SI is
Devices can be interconnected easily to expand word and
held HIGH during reset, data will be loaded at the rising
bit dimensions. All output pins are directly opposite the
edge of the MR signal.
corresponding input pins thus simplifying board layout in
expanded applications.
Shift-out control (SO)
A LOW-to-HIGH transition of SO causes the DOR flags to
INPUTS AND OUTPUTS
go LOW. A HIGH-to-LOW transition of SO causes
upstream data to move into the output stage, and empty
Data inputs (D to D )
0 8
locations to move towards the input stage (bubble-up).
As there is no weighting of the inputs, any input can be
assigned as the MSB. The size of the FIFO memory can
Output enable (OE)
be reduced from the 9 64 configuration, i.e. 8 64,
The outputs Q to Q are enabled when OE = LOW. When
0 8
7 64, down to 1 64, by tying unused data input pins to
OE = HIGH the outputs are in the high impedance
V or GND.
CC
OFF-state.
December 1990 2