DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 IDT74SSTUBF32866B design of the IDT74SSTUBF32866B must ensure that the Description outputs will remain low, thus ensuring no glitches on the output. This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS All clock and data inputs are compatible with the JEDEC and CSR inputs are high. If either DCS and CSR input is standard for SSTL 18. The control inputs are LVCMOS. All low, the Qn outputs will function normally. The RESET input outputs are 1.8-V CMOS drivers that have been optimized has priority over the DCS and CSR control and will force the to drive the DDR-II DIMM load. IDT74SSTUBF32866B outputs low. If the DCS-control functionality is not desired, operates from a differential clock (CLK and CLK). Data are then the CSR input can be hardwired to ground, in which registered at the crossing of CLK going high, and CLK case, the setup-time requirement for DCS would be the going low. same as for the other D data inputs. Package options The C0 input controls the pinout configuration of the 1:2 include 96-ball LFBGA (MO-205CC). pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). Features A - Pair Configuration (C01 = 0, C11 = 1 and C02 = 0, C12 = 1) 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check functionality Parity that arrives one cycle after the data input to which it Supports SSTL 18 JEDEC specification on data inputs applies is checked on the PAR IN of the first register. The and outputs second register produces to PPO and QERR signals. The Supports LVCMOS switching levels on C0, C1, and QERR of the first register is left floating. The valid error RESET inputs information is latched on the QERR output of the second Low voltage operation: VDD = 1.7V to 1.9V register. If an error occurs QERR is latched low for two Available in 96-ball LFBGA package cycles or until RESET is low. B - Single Configuration (C0 = 0, C1 = 0) The device supports low-power standby operation. When the RESET input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock Applications and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all DDR2 Memory Modules outputs are forced low. The LVCMOS RESET and Cn inputs Provides complete DDR DIMM solution with must always be held at a valid logic high or low level. To ICS98ULPA877A or IDTCSPUA877A ensure defined outputs from the register before a stable Ideal for DDR2 667 and 800 clock has been supplied, RESET must be held in the low state during power up. In the DDR-II RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 1 IDT74SSTUBF32866B 7067/13IDT74SSTUBF32866B 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 COMMERCIAL TEMPERATURE GRADE Functional Block Diagram for 1:1 Mode (Positive Logic) RESET CLK CLK VREF DCKE D C1 QCKEA R DODT D C1 QOTDA R DCS 1D C1 QCSA R CSR D1 O 1 1D Q1A C1 (1) Q1B R TO 21 OTHER CHANNELS NOTE: 1. Disabled in 1:1 configuration. 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 2 IDT74SSTUBF32866B 7067/13