X-On Electronics has gained recognition as a prominent supplier of 74HC7046AN,112 Phase Locked Loops - PLL across the USA, India, Europe, Australia, and various other global locations. 74HC7046AN,112 Phase Locked Loops - PLL are a product manufactured by NXP. We provide cost-effective solutions for Phase Locked Loops - PLL, ensuring timely deliveries around the world.

74HC7046AN,112 NXP

74HC7046AN,112 electronic component of NXP
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Part No.74HC7046AN,112
Manufacturer: NXP
Category: Phase Locked Loops - PLL
Description: Phase Locked Loops - PLL PHASE LOCKED LOOP
Datasheet: 74HC7046AN,112 Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)
1: USD 1.1466 ea
Line Total: USD 1.15 
Availability - 0
MOQ: 1  Multiples: 1
Pack Size: 1
Availability Price Quantity
0
Ship by Thu. 28 Nov to Wed. 04 Dec
MOQ : 1
Multiples : 1
1 : USD 1.1466
10 : USD 1.1349
50 : USD 1.0764
250 : USD 0.9477
500 : USD 0.9009
1000 : USD 0.8892

   
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We are delighted to provide the 74HC7046AN,112 from our Phase Locked Loops - PLL category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the 74HC7046AN,112 and other electronic components in the Phase Locked Loops - PLL category and beyond.

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT7046A Phase-locked-loop with lock detector December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Phase-locked-loop with lock detector 74HC/HCT7046A FEATURES amplifiers. With a passive low-pass SIG (pin 14) or COMP (pin 3) IN IN filter, the 7046 forms a second-order inputs between the HC and HCT Low power consumption loop PLL. The excellent VCO linearity versions. Centre frequency up to 17 MHz is achieved by the use of linear (typ.) at V = 4.5 V CC op-amp techniques. Phase comparators Choice of two phase comparators: The signal input (SIG ) can be IN VCO EXCLUSIVE-OR directly coupled to the self-biasing edge-triggered JK flip-flop The VCO requires one external amplifier at pin 14, provided that the Excellent VCO frequency linearity capacitor C1 (between C1 and C1 ) signal swing is between the standard A B and one external resistor R1 HC family input logic levels. VCO-inhibit control for ON/OFF (between R and GND) or two Capacitive coupling is required for keying and for low standby power 1 external resistors R1 and R2 signals with smaller swings. consumption (between R and GND, and R and 1 2 Minimal frequency drift GND). Resistor R1 and capacitor C1 Phase comparator 1 (PC1) Operation power supply voltage determine the frequency range of the This is an EXCLUSIVE-OR network. range: VCO. Resistor R2 enables the VCO The signal and comparator input VCO section 3.0 to 6.0 V to have a frequency offset if required. frequencies (f ) must have a 50% duty digital section 2.0 to 6.0 V i The high input impedance of the VCO factor to obtain the maximum locking Zero voltage offset due to op-amp simplifies the design of low-pass range. The transfer characteristic of buffering filters by giving the designer a wide PC1, assuming ripple (f =2f ) is r i Output capability: standard choice of resistor/capacitor ranges. In suppressed, order not to load the low-pass filter, a I category: MSI is: CC demodulator output of the VCO input V CC voltage is provided at pin 10 V =() ----------- DEMOUT SIGIN COMPIN GENERAL DESCRIPTION (DEM ). In contrast to conventional OUT techniques where the DEM OUT The 74HC/HCT7046 are high-speed voltage is one threshold voltage lower Si-gate CMOS devices and are than the VCO input voltage, here the specified in compliance with JEDEC where V is the demodulator DEM voltage equals that of the DEMOUT OUT standard no. 7. output at pin 10 VCO input. If DEM is used, a load OUT The 74HC/HCT7046 are resistor (R ) should be connected S V =V (via low-pass DEMOUT PC1OUT phase-locked-loop circuits that from DEM to GND if unused, OUT filter). comprise a linear voltage-controlled DEM should be left open. The OUT oscillator (VCO) and two different The phase comparator gain VCO output (VCO ) can be OUT phase comparators (PC1 and PC2) is: connected directly to the comparator with a common signal input amplifier V input (COMP ), or connected via a IN CC K= ()Vr . ----------- and a common comparator input. p frequency-divider. The VCO output signal has a duty factor of 50% A lock detector is provided and this (maximum expected deviation 1%), if gives a HIGH level at pin 1 (LD) when The average output voltage from the VCO input is held at a constant the PLL is locked. The lock detector PC1, fed to the VCO input via the DC level. A LOW level at the inhibit capacitor must be connected low-pass filter and seen at the input (INH) enables the VCO and between pin 15 (C ) and pin 8 LD demodulator output at pin 10 demodulator, while a HIGH level turns (GND). The value of the C capacitor LD both off to minimize standby power (V ), is the resultant of the DEMOUT can be determined, using information phase differences of signals (SIG ) consumption. IN supplied in Fig.32. The input signal and the comparator input (COMP ) IN can be directly coupled to large The only difference between the HC as shown in Fig.6. The average of voltage signals, or indirectly coupled and HCT versions is the input level V is equal to 1/2 V when DEMOUT CC (with a series capacitor) to small specification of the INH input. This there is no signal or noise at SIG IN voltage signals. A self-bias input input disables the VCO section. The and with this input the VCO oscillates circuit keeps small voltage signals comparators sections are identical, at the centre frequency (f ). Typical o within the linear region of the input so that there is no difference in the December 1990 2

Tariff Desc

8542.31.00 51 No ..Application Specific (Digital) Integrated Circuits (ASIC)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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