Complete, High Speed 16-Bit A/D Converters AD1376/AD1377 Digital output data is provided in parallel form with FEATURES corresponding clock and status outputs. All digital inputs and Complete 16-bit converters with reference and clock outputs are TTL-compatible. 0.003% maximum nonlinearity No missing codes to 14 bits over temperature For the AD1376, the serial output function is no longer Fast conversion available after date code 0111. For the AD1377, the serial output 17 s to 16 bits (AD1376) function is no longer available after date code 0210. The option 10 s to 16 bits (AD1377) of applying an external clock on the CONVERT START pin to Short cycle capability slow down the internally set conversion time is no longer Adjustable clock rate supported for either part. Parallel outputs Low power PRODUCT HIGHLIGHTS 645 mW typical (AD1376) 1. The AD1376/AD1377 provide 16-bit resolution with a 585 mW typical (AD1377) maximum linearity error of 0.003% (1/2 LSB14) at 25C. Industry-standard pinout 2. The AD1376 conversion time is 14 s (typical) short cycled GENERAL DESCRIPTION to 14 bits, and 16 s to 16 bits. The AD1376/AD1377 are high resolution, 16-bit analog-to- digital converters with internal reference, clock, and laser- 3. The AD1377 conversion time is 8 s (typical) short cycled trimmed thin-film applications resistors. The AD1376/AD1377 to 14 bits, and 9 s to 16 bits. are excellent for use in high resolution applications requiring 4. Two binary codes are available on the digital output. They moderate speed and high accuracy or stability over commercial are CSB (complementary straight binary) for unipolar input temperature ranges (0C to 70C). They are packaged in voltage ranges and COB (complementary offset binary) for compact 32-lead, ceramic seam-sealed (hermetic), dual in-line bipolar input ranges. Complementary twos complement packages (DIP). Thin-film scaling resistors provide bipolar (CTC) coding may be obtained by inverting Pin 1 (MSB). input ranges of 2.5 V, 5 V, and 10 V and unipolar input 5. The AD1376/AD1377 include internal reference and clock ranges of 0 V to +5 V, 0 V to +10 V, and 0 V to +20 V. with external clock rate adjust pin, and parallel digital outputs. FUNCTIONAL BLOCK DIAGRAM (MSB) BIT 1 1 32 SHORT CYCLE BIT 2 2 31 CONVERT START AD1376/AD1377 BIT 3 3 30 +5V DC SUPPLY V REFERENCE L BIT 4 4 29 GAIN ADJUST BIT 5 5 28 +15V DC SUPPLY V CC BIT 6 6 27 COMPARATOR IN 7.5k BIT 7 7 26 BIPOLAR OFFSET BIT 8 8 25 +10V 3.75k 3.75k BIT 9 9 24 +20V BIT 10 10 23 CLK RATE CTRL BIT 11 11 22 ANALOG COMMON 16-BIT SAR BIT 12 12 21 15V DC SUPPLY V EE (LSB FOR 13 BITS) BIT 13 13 20 CLOCK OUT (LSB FOR 14 BITS) BIT 14 14 19 DIGITAL COMMON COMPARATOR CLOCK BIT 15 15 18 STATUS BIT 16 16 17 NC Figure 1. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Specifications subject to change without notice. No license is granted by implication Tel: 781.329.4700 www.analog.com or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Fax: 781.481.3113 2005 Analog Devices, Inc. All rights reserved. 16-BIT DAC 00699-001AD1376/AD1377 TABLE OF CONTENTS Specifications..................................................................................... 3 Input Scaling ..................................................................................7 Absolute Maximum Ratings............................................................ 5 Calibration (14-Bit Resolution Examples).................................8 ESD Caution.................................................................................. 5 Grounding, Decoupling, and Layout Considerations ..............9 Description of Operation ................................................................ 6 Clock Rate Control........................................................................9 Gain Adjustment .......................................................................... 6 High Resolution Data Acquisition System.............................. 10 Zero Offset Adjustment............................................................... 6 Applications..................................................................................... 11 Timing............................................................................................ 7 Outline Dimensions ....................................................................... 12 Digital Output Data ..................................................................... 7 Ordering Guide .......................................................................... 12 REVISION HISTORY 6/05Rev. C to Rev. D Updated Format..................................................................Universal Updated Outline Dimensions ....................................................... 12 6/03Rev. B to Rev. C Removed Serial Output Function and Adjustable Clock Rate ........................................................Universal Updated Format..................................................................Universal Changes to General Description .................................................... 1 Changes to Product Highlights....................................................... 1 Changes to Functional Block Diagram.......................................... 1 Inserted ESD Warning ..................................................................... 3 Change to Ordering Guide.............................................................. 3 Change to Figure 7 ........................................................................... 5 Deleted text from Digital Output Data.......................................... 5 Deleted Figure 9 and Renumbered Remainder of Figures.......... 5 Deleted the Using the AD1376 or AD1377 at Slower Conversion Times Section............................................... 8 Deleted Figure 16.............................................................................. 8 Change to Figure 13 ......................................................................... 9 Change to Figure 14 ......................................................................... 9 Updated Outline Dimensions ....................................................... 10 Rev. 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