Complete 12-Bit 1.25 MSPS a Monolithic A/D Converter AD1671 FEATURES FUNCTIONAL BLOCK DIAGRAM Conversion Time: 800 ns SHA 1.25 MHz Throughput Rate V V V OUT UPO/BPO ENCODE CC ACOM DCOM EE LOGIC Complete: On-Chip Sample-and-Hold Amplifier and 5k S/H AIN1 Voltage Reference RANGE Low Power Dissipation: 570 mW AIN2 SELECT X4 5k No Missing Codes Guaranteed Signal-to-Noise Plus Distortion Ratio COARSE 8-BIT 3-BIT 3-BIT DAC DAC 4-BIT LADDER FLASH FLASH f = 100 kHz: 70 dB IN MATRIX FLASH Pin Configurable Input Voltage Ranges 3 3 4 FINE Twos Complement or Offset Binary Output Data 4-BIT 28-Pin DIP and 28-Pin Surface Mount Package REF IN CORRECTION LOGIC FLASH 2.5V Out of Range Indicator 8 4 REF OUT REF LATCHES AD1671 12 REF COM OTR MSB DAV BIT 1 12 PRODUCT DESCRIPTION The performance of the AD1671 is made possible by using high The AD1671 is a monolithic 12-bit, 1.25 MSPS analog-to- speed, low noise bipolar circuitry in the linear sections and low digital converter with an on-board, high performance sample- power CMOS for the logic sections. Analog Devices ABCMOS-1 and-hold amplifier (SHA) and voltage reference. The AD1671 process provides both high speed bipolar and 2-micron CMOS guarantees no missing codes over the full operating tempera- devices on a single chip. Laser trimmed thin-film resistors are ture range. The combination of a merged high speed bipolar/ used to provide accuracy and temperature stability. CMOS process and a novel architecture results in a combi- The AD1671 is available in two performance grades and three nation of speed and power consumption far superior to pre- temperature ranges. The AD1671J and K grades are available viously available hybrid implementations. Additionally, the over the 0C to +70C temperature range. The AD1671A grade greater reliability of monolithic construction offers improved is available over the 40C to +85C temperature range. The system reliability and lower costs than hybrid designs. AD1671S grade is available over the 55C to +125C tempera- The fast settling input SHA is equally suited for both multi- ture range. plexed systems that switch negative to positive full-scale voltage levels in successive channels and sampling inputs at PRODUCT HIGHLIGHTS frequencies up to and beyond the Nyquist rate. The AD1671 The AD1671 offers a complete single chip sampling 12-bit, provides both reference output and reference input pins, al- 1.25 MSPS analog-to-digital conversion function in a 28-pin lowing the on-board reference to serve as a system reference. package. An external reference can also be chosen to suit the dc accu- The AD1671 at 570 mW consumes a fraction of the power of racy and temperature drift requirements of the application. currently available hybrids. The AD1671 uses a subranging flash conversion technique, An OUT OF RANGE output bit indicates when the input sig- with digital error correction for possible errors introduced in nal is beyond the AD1671s input range. the first part of the conversion cycle. An on-chip timing gen- Input signal ranges are 0 V to +5 V unipolar or 5 V bipolar, erator provides strobe pulses for each of the four internal selected by pin strapping, with an input resistance of 10 k. flash cycles. A single ENCODE pulse is used to control the The input signal range can also be pin strapped for 0 V to +2.5 V converter. The digital output data is presented in twos unipolar or 2.5 V bipolar with an input resistance of 10 M. complement or offset binary output format. An out-of-range signal indicates an overflow condition. It can be used with Output data is available in unipolar, bipolar offset or bipolar the most significant bit to determine low or high overflow. twos complement binary format. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703AD1671SPECIFICATIONS (T to T with V = +5 V 6 5%, V = +5 V 6 10%, V = 5 V 6 5%, unless otherwise noted) MIN MAX CC LOGIC EE DC SPECIFICATIONS AD1671J/A/S AD1671K Parameter Min Typ Max Min Typ Max Units RESOLUTION 12 12 Bits CONVERSION TIME 800 800 ns ACCURACY Integral Nonlinearity (INL) 1.5 2.5 0.7 2.5 LSB (S Grade) 3.0 Differential Nonlinearity (DNL) 11 12 Bits No Missing Codes 11 Bits Guaranteed 12 Bits Guaranteed 1 Unipolar Offsets (+25C) 9 9 LSB 1 Bipolar Zero (+25C) 10 10 LSB 1, 2 Gain Error (+25C) 0.1 0.35 0.1 0.35 % FSR 3 TEMPERATURE COEFFICIENTS Unipolar Offset 25 25 ppm/C (S Grade) 25 Bipolar Zero 25 25 ppm/C (S Grade) 30 3 Gain Error 30 30 ppm/C (S Grade) 40 4 Gain Error 20 20 ppm/C 5 POWER SUPPLY REJECTION V (+5 V 0.25 V) 4 4 LSB CC (S Grade) 5 V (+5 V 0.25 V) 4 4 LSB LOGIC (S Grade) 5 V (5 V 0.25 V) 4 4 LSB EE (S Grade) 5 ANALOG INPUT Input Ranges Bipolar 2.5 +2.5 2.5 +2.5 Volts 5.0 +5.0 5.0 +5.0 Volts Unipolar 0 +2.5 0 +2.5 Volts 0 +5.0 0 +5.0 Volts Input Resistance (0 V to +2.5 V or 2.5 V Range) 10 10 M (0 V to +5.0 V or 5 V Range) 8 10 12 8 10 12 k Input Capacitance 10 10 pF Aperture Delay 15 15 ns Aperture Jitter 20 20 ps INTERNAL VOLTAGE REFERENCE Output Voltage 2.475 2.5 2.525 2.475 2.5 2.525 Volts Output Current Unipolar Mode +2.5 +2.5 mA Bipolar Mode +1.0 +1.0 mA LOGIC INPUTS High Level Input Voltage, V 2.0 2.0 Volts IH Low Level Input Voltage, V 0.8 0.8 Volts IL High Level Input Current, I (V = V ) 10 +10 10 +10 A IH IN LOGIC Low Level Input Current, I (V = 0 V) 10 +10 10 +10 A LL IN Input Capacitance, C 55pF IN LOGIC OUTPUTS High Level Output Voltage, V (I = 0.5 mA) 2.4 2.4 Volts OH OH Low Level Output Voltage, V (I = 1.6 mA) 0.4 0.4 Volts OL OL POWER SUPPLIES Operating Voltages V +4.75 +5.25 +4.75 +5.25 Volts CC V +4.5 +5.5 +4.5 +5.5 Volts LOGIC V 4.75 5.25 4.75 5.25 Volts EE Operating Current I 55 68 55 68 mA CC 6 I 35 3 5 mA LOGIC I 55 68 55 68 mA EE POWER CONSUMPTION 570 750 570 750 mW TEMPERATURE RANGE (SPECIFIED) J/K 0 +70 0 +70 C A 40 +85 40 +85 C S 55 +125 55 +125 C NOTES 1 Adjustable to zero with external potentiometers. 2 Includes internal voltage reference error. 3 +25C to T and +25C to T MIN MAX 4 Excludes internal reference drift. 5 Change in gain error as a function of the dc supply voltage. 6 Tested under static conditions. See Figure 15 for typical curve of I vs. load capacitance at maximum t . LOGIC C Specifications subject to change without notice. 2 REV. B