192 kHz Stereo Asynchronous a Sample Rate Converter AD1895 FEATURES FUNCTIONAL BLOCK DIAGRAM Automatically Senses Sample Frequencies RESET VDD IO VDD CORE No Programming Required Attenuates Sample Clock Jitter AD1895 3.3 V to 5 V Input and 3.3 V Core Supply Voltages MUTE IN Accepts 16-/18-/20-/24-Bit Data FS OUT SDATA I FIFO SDATA O Up to 192 kHz Sample Rate FS SCLK I IN SCLK O LRCLK I LRCLK O Input/Output Sample Ratios from 7.75:1 to 1:8 SERIAL Bypass Mode SMODE IN 0 INPUT TDM IN SMODE IN 1 SERIAL Multiple AD1895 TDM Daisy-Chain Mode SMODE IN 2 OUTPUT FIR DIGITAL SMODE OUT 0 128 dB Signal-to-Noise and Dynamic Range FILTER PLL SMODE OUT 1 BYPASS (A-Weighted, 20 Hz to 20 kHz BW) MUTE OUT Up to 122 dB THD + N WLNGTH OUT 0 Linear Phase FIR Filter WLNGTH OUT 1 CLOCK DIVIDER ROM Hardware Controllable Soft Mute Supports 256 f , 512 f , or 768 f Master Mode S S S MCLK IN MMODE 0 MMODE 2 Clock MCLK OUT MMODE 1 Flexible 3-Wire Serial Data Port with Left-Justified, 2 I S, Right-Justified (16-, 18-, 20-, 24-Bit), and TDM Serial Port Modes a digital signal processor. The serial output data is dithered down Master/Slave Input and Output Modes to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is 28-Lead SSOP Plastic Package selected. The AD1895 sample rate converts the data from the serial input port to the sample rate of the serial output port. The APPLICATIONS sample rate at the serial input port can be asynchronous with Home Theater Systems, Automotive Audio Systems, respect to the output sample rate of the output serial port. The DVD, DVD-R, CD-R, Set-Top Boxes, Digital Audio master clock to the AD1895, MCLK, can be asynchronous to Effects Processors both the serial input and output ports. MCLK can either be generated off-chip or on-chip by the AD1895 master clock oscillator. Since MCLK can be asynchronous to the PRODUCT OVERVIEW input or output serial ports, a crystal can be used to generate The AD1895 is a 24-bit, high performance, single-chip, second MCLK internally to reduce noise and EMI emissions on the generation asynchronous sample rate converter. Based upon board. When MCLK is synchronous to either the output or input Analog Devices experience with its first asynchronous sample serial port, the AD1895 can be configured in a master mode where rate converter, the AD1890, the AD1895 offers improved perfor- MCLK is divided down and used to generate the left/right mance and additional features. This improved performance and bit clocks for the serial port that is synchronous to MCLK. includes a THD + N range of 115 dB to 122 dB depending The AD1895 supports master modes of 256 f , 512 f , and S S on sample rate and input frequency, 128 dB (A-Weighted) 768 f for both input and output serial ports. S dynamic range, 192 kHz sampling frequencies for both input and Conceptually, the AD1895 interpolates the serial input data by output sample rates, improved jitter rejection, and 1:8 upsampling 20 a rate of 2 and samples the interpolated data stream by the and 7.75:1 downsampling ratios. Additional features include 20 output sample rate. In practice, a 64-tap FIR filter with 2 more serial formats, a bypass mode, and better interfacing to polyphases, a FIFO, a digital servo loop that measures the time digital signal processors. difference between input and output samples within 5 ps, and a The AD1895 has a 3-wire interface for the serial input and digital circuit to track the sample rate ratio are used to perform 2 output ports that supports left-justified, I S, and right-justified the interpolation and output sampling. Refer to the Theory of (16-, 18-, 20-, 24-bit) modes. Additionally, the serial output Operation section. The digital servo loop and sample rate ratio port supports TDM Mode for daisy-chaining multiple AD1895s to circuit automatically track the input and output sample rates. (continued on page 15) REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. use, nor for any infringements of patents or other rights of third parties that Tel: 781/329-4700 www.analog.com may result from its use. No license is granted by implication or otherwise Fax: 781/326-8703 Analog Devices, Inc., 2002 under any patent or patent rights of Analog Devices.AD1895SPECIFICATIONS TEST CONDITIONS, UNLESS OTHERWISE NOTED. Supply Voltages VDD CORE 3.3 V VDD IO 5.0 V or 3.3 V Ambient Temperature 25C Input Clock 30.0 MHz Input Signal 1.000 kHz, 0 dBFS Measurement Bandwidth 20 to f /2 Hz S OUT Word Width . 24 Bits Load Capacitance 50 pF Input Voltage High . 2.4 V Input Voltage Low 0.8 V DIGITAL PERFORMANCE (VDD CORE = 3.3 V 5%, VDD IO = 5.0 V 10%) Parameter Min Typ Max Unit RESOLUTION 24 Bits SAMPLE RATE MCLK IN = 30 MHz 6 215 kHz 1 SAMPLE RATE ( OTHER MASTER CLOCKS) MCLK IN/5000 f < MCLK IN/138 kHz S MAX SAMPLE RATE RATIOS Upsampling 1:8 Downsampling 7.75:1 2 DYNAMIC RANGE (20 Hz to f /2, 1 kHz, 60 dBFS Input) A-Weighted S OUT 44.1 kHz: 48 kHz 128 dB 48 kHz: 44.1 kHz 128 dB 48 kHz: 96 kHz 128 dB 44.1 kHz: 192 kHz 128 dB 96 kHz: 48 kHz 127 dB 192 kHz: 32 kHz 127 dB (20 Hz to f /2, 1 kHz, 60 dBFS Input) No Filter S OUT 44.1 kHz: 48 kHz 125 dB 48 kHz: 44.1 kHz 125 dB 48 kHz: 96 kHz 125 dB 44.1 kHz: 192 kHz 125 dB 96 kHz: 48 kHz 124 dB 192 kHz: 32 kHz 124 dB 2 TOTAL HARMONIC DISTORTION + NOISE (20 Hz to f /2, 1 kHz, 0 dBFS Input) No Filter S OUT 3 Worst-Case (48 kHz: 96 kHz) 115 dB 44.1 kHz: 48 kHz 120 dB 48 kHz: 44.1 kHz 119 dB 48 kHz: 96 kHz 118 dB 44.1 kHz: 192 kHz 120 dB 96 kHz: 48 kHz 122 dB 192 kHz: 32 kHz 122 dB INTERCHANNEL GAIN MISMATCH 0.0 dB INTERCHANNEL PHASE DEVIATION 0.0 Degrees MUTE ATTENUATION (24 BITS WORD WIDTH)(A-WEIGHT) 127 dB NOTES 1 Lower sampling rates than those given by this formula are possible, but the jitter rejection will decrease. 2 Refer to the Typical Performance Characteristics section for DNR and THD + N numbers over a wide range of input and output sample rates. 3 For any other ratio, minimum THD + N will be better than 115 dB. Please refer to detailed performance plots. Specifications subject to change without notice. REV. B 2