192 kHz Stereo Asynchronous
a
Sample Rate Converter
AD1896
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Automatically Senses Sample Frequencies
GRPDLYS RESET VDD_IO VDD_CORE
No Programming Required
Attenuates Sample Clock Jitter
AD1896
MUTE_I
3.3 V5 V Input and 3.3 V Core Supply Voltages
Accepts 16-/18-/20-/24-Bit Data FS
OUT
SDATA_I
FIFO SDATA_O
FS
Up to 192 kHz Sample Rate SCLK_I IN
SCLK_O
LRCLK_I
LRCLK_O
Input/Output Sample Ratios from 7.75:1 to 1:8
SERIAL
SMODE_IN_0 INPUT
Bypass Mode
TDM_IN
SMODE_IN_1
SERIAL
Multiple AD1896 TDM Daisy-Chain Mode
SMODE_IN_2
OUTPUT
FIR SMODE_O_0
DIGITAL
Multiple AD1896 Matched-Phase Mode FILTER
SMODE_O_1
PLL
BYPASS
142 dB Signal-to-Noise and Dynamic Range
MUTE_O
(A-Weighted, 20 Hz20 kHz BW)
WLNGTH_O_0
WLNGTH_O_1
Up to 133 dB THD + N CLOCK DIVIDER ROM
Linear Phase FIR Filter
Hardware Controllable Soft Mute
MCLK_I MSMODE_0 MSMODE_2
Supports 256 f , 512 f , or 768 f Master
S S S
MCLK_O
MSMODE_1
Mode Clock
Flexible 3-Wire Serial Data Port with Left-Justified,
2
I S, Right-Justified (16-,18-, 20-, 24-Bits), and
port supports TDM mode for daisy-chaining multiple AD1896s to
TDM Serial Port Modes
a digital signal processor. The serial output data is dithered down
Master/Slave Input and Output Modes
to 20, 18, or 16 bits when 20-, 18-, or 16-bit output data is se-
28-Lead SSOP Plastic Package
lected. The AD1896 sample rate converts the data from the
serial input port to the sample rate of the serial output port. The
APPLICATIONS
sample rate at the serial input port can be asynchronous with
Home Theater Systems, Studio Digital Mixers,
respect to the output sample rate of the output serial port. The
Automotive Audio Systems, DVD, Set-Top Boxes,
master clock to the AD1896, MCLK, can be asynchronous to
Digital Audio Effects Processors, Studio-to-Transmitter
both the serial input and output ports.
Links, Digital Audio Broadcast Equipment,
DigitalTape Varispeed Applications
MCLK can be generated either off-chip or on-chip by the AD1896
master clock oscillator. Since MCLK can be asynchronous to the
input or output serial ports, a crystal can be used to generate
MCLK internally to reduce noise and EMI emissions on the
PRODUCT OVERVIEW
board. When MCLK is synchronous to either the output or input
The AD1896 is a 24-bit, high performance, single-chip, second-
serial port, the AD1896 can be configured in a master mode where
generation asynchronous sample rate converter. Based on Analog
MCLK is divided down and used to generate the left/right
Devices experience with its first asynchronous sample rate
and bit clocks for the serial port that is synchronous to MCLK.
converter, the AD1890, the AD1896 offers improved performance
The AD1896 supports master modes of 256 f , 512 f ,
S S
and additional features. This improved performance includes a
and 768 f for both input and output serial ports.
S
THD + N range of 117 dB to 133 dB depending on the sample
rate and input frequency, 142 dB (A-Weighted) dynamic range,
Conceptually, the AD1896 interpolates the serial input data by
20
192 kHz sampling frequencies for both input and output sample
a rate of 2 and samples the interpolated data stream by the
20
rates, improved jitter rejection, and 1:8 upsampling and 7.75:1
output sample rate. In practice, a 64-tap FIR filter with 2
downsampling ratios. Additional features include more serial
polyphases, a FIFO, a digital servo loop that measures the time
formats, a bypass mode, better interfacing to digital signal pro-
difference between the input and output samples within 5 ps,
cessors, and a matched-phase mode.
and a digital circuit to track the sample rate ratio are used to
perform the interpolation and output sampling. Refer to the
The AD1896 has a 3-wire interface for the serial input and
2
Theory of Operation section. The digital servo loop and sample
output ports that supports left-justified, I S, and right-justified
rate ratio circuit automatically track the input and output
(16-, 18-, 20-, 24-bit) modes. Additionally, the serial output
sample rates.
(Continued on Page 17)
REV. A
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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise
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under any patent or patent rights of Analog Devices. Trademarks and
Fax: 781/326-8703 2003 Analog Devices, Inc. All rights reserved.
registered trademarks are the property of their respective companies.AD1896SPECIFICATIONS
TEST CONDITIONS, UNLESS OTHERWISE NOTED.
Supply Voltages
VDD_CORE 3.3 V
VDD_IO 5.0 V or 3.3 V
Ambient Temperature 25C
Input Clock 30.0 MHz
Input Signal 1.000 kHz, 0 dBFS
Measurement Bandwidth 20 to f /2 Hz
S_OUT
Word Width 24 Bits
Load Capacitance 50 pF
Input Voltage High 2.4 V
Input Voltage Low 0.8 V
Specifications subject to change without notice.
DIGITAL PERFORMANCE (VDD_CORE = 3.3 V 5%, VDD_IO = 5.0 V 10%)
Parameter Min Typ Max Unit
Resolution 24 Bits
Sample Rate @ MCLK_I = 30 MHz 6 215 kHz
1
Sample Rate (@ Other Master Clocks) MCLK_I/5000 f < MCLK_I/138 kHz
S
Sample Rate Ratios
Upsampling 1:8
Downsampling (Short GRPDLYS) 7.75:1
Downsampling (Long GRPDLYS) 7.0:1
2
Dynamic Range
(20 Hz to f /2, 1 kHz, 60 dBFS Input) A-Weighted
S_OUT
Worst-Case (192 kHz:48 kHz) 132 dB
44.1 kHz:48 kHz 142 dB
48 kHz:44.1 kHz 141 dB
48 kHz:96 kHz 142 dB
44.1 kHz:192 kHz 141.5 dB
96 kHz:48 kHz 140 dB
192 kHz:32 kHz 140 dB
(20 Hz to f /2, 1 kHz, 60 dBFS Input) No Filter
S_OUT
Worst-Case (192 kHz:48 kHz) 132 dB
44.1 kHz:48 kHz 139 dB
48 kHz:44.1 kHz 139 dB
48 kHz:96 kHz 139 dB
44.1 kHz:192 kHz 137 dB
96 kHz:48 kHz 137 dB
192 kHz:32 kHz 138 dB
2
Total Harmonic Distortion + Noise
(20 Hz to f /2, 1 kHz, 0 dBFS Input) No Filter
S_OUT
3
Worst-Case (32 kHz:48 kHz) 117 dB
44.1 kHz:48 kHz 123 dB
48 kHz:44.1 kHz 124 dB
48 kHz:96 kHz 120 dB
44.1 kHz:192 kHz 123 dB
96 kHz:48 kHz 132 dB
192 kHz:32 kHz 133 dB
Interchannel Gain Mismatch 0.0 dB
Interchannel Phase Deviation 0.0 Degrees
Mute Attenuation (24 Bits Word Width) (A-Weighted) 144 dB
NOTES
1
Lower sampling rates than given by this formula are possible, but the jitter rejection will decrease.
2
Refer to the Typical Performance Characteristics section for DNR and THD + N numbers over wide range of input and output sample rates.
3
For any other sample rate ratio, the minimum THD + N will be better than 117 dB. Please refer to detailed performance plots.
Specifications subject to change without notice.
2 REV. A