2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec AD1928 FEATURES GENERAL DESCRIPTION PLL-generated or direct master clock The AD1928 is a high performance, single-chip codec that Low EMI design provides two analog-to-digital converters (ADCs) with differ- 108 dB DAC/107 dB ADC dynamic range and SNR ential input and eight digital-to-analog converters (DACs) with 94 dB THD + N single-ended output using the Analog Devices, Inc., patented 3.3 V single supply multibit sigma-delta (-) architecture. An SPI port is included, Tolerance for 5 V logic inputs allowing a microcontroller to adjust volume and many other Supports 24 bits and 8 kHz to 192 kHz sample rates parameters. The AD1928 operates from 3.3 V digital and analog Differential ADC input supplies. The AD1928 is available in a 48-lead (single-ended Single-ended DAC output output) LQFP package. Other members of this family include a Log volume control with autoramp function differential DAC output version. SPI controllable for flexibility The AD1928 is designed for low EMI. This consideration is Software-controllable clickless mute apparent in both the system and circuit design architectures. Software power-down By using the on-board PLL to derive the master clock from the 2 Right-justified, left-justified, I S-justified, and TDM modes LR clock or from an external crystal, the AD1928 eliminates the Master and slave modes up to 16-channel input/output need for a separate high frequency master clock and can be 48-lead LQFP used with a suppressed bit clock. The digital-to-analog and analog-to-digital converters are designed using the latest APPLICATIONS Analog Devices continuous time architectures to further Automotive audio systems minimize EMI. By using 3.3 V supplies, power consumption is Home theater systems minimized, further reducing emissions. Set-top boxes Digital audio effects processors FUNCTIONAL BLOCK DIAGRAM DIGITAL AUDIO INPUT/OUTPUT AD1928 SERIAL DATA PORT DAC DAC SDATA SDATA DAC OUT IN QUAD DIGITAL ADC DEC ANALOG CLOCKS FILTER DAC ANALOG FILTER AUDIO AND AUDIO 48kHz/ INPUTS VOLUME OUTPUTS DAC 96kHz/ ADC CONTROL TIMING MANAGEMENT 192kHz AND CONTROL DAC (CLOCK AND PLL) DAC DAC CONTROL PORT PRECISION SPI VOLTAGE REFERENCE CONTROL DATA INPUT/OUTPUT Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Fax: 781.461.3113 2007-2011 Analog Devices, Inc. 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OBSOLETE 06623-001AD1928 TABLE OF CONTENTS Features .............................................................................................. 1 Analog-to-Digital Converters (ADCs).................................... 13 Applications....................................................................................... 1 Digital-to-Analog Converters (DACs) .................................... 13 General Description ......................................................................... 1 Clock Signals............................................................................... 13 Functional Block Diagram .............................................................. 1 Reset and Power-Down ............................................................. 14 Revision History ............................................................................... 2 Serial Control Port ..................................................................... 14 Specifications..................................................................................... 3 Power Supply and Voltage Reference....................................... 15 Test Conditions............................................................................. 3 Serial Data PortsData Format............................................... 15 Analog Performance Specifications ........................................... 3 Time-Division Multiplexed (TDM) Modes............................ 15 Crystal Oscillator Specifications................................................. 5 Daisy-Chain Mode..................................................................... 19 Digital Input/Output Specifications........................................... 5 Control Registers ............................................................................ 24 Power Supply Specifications........................................................ 5 Definitions................................................................................... 24 Digital Filters................................................................................. 6 PLL and Clock Control Registers............................................. 24 Timing Specifications .................................................................. 6 DAC Control Registers.............................................................. 25 Absolute Maximum Ratings............................................................ 8 ADC Control Registers.............................................................. 27 Thermal Resistance ...................................................................... 8 Additional Modes....................................................................... 29 ESD Caution.................................................................................. 8 Application Circuits ....................................................................... 30 Pin Configuration and Function Descriptions............................. 9 Outline Dimensions....................................................................... 31 Typical Performance Characteristics ........................................... 11 Ordering Guide .......................................................................... 31 Theory of Operation ...................................................................... 13 REVISION HISTORY 7/11Rev. A to Rev. B 2 Deleted References to I C ............................................. Throughout Changes to Table 10, DSDATAx/ASDATAx Pin Descriptions... 9 2/11Rev. 0 to Rev. A Change to Table 2, Introductory Text ............................................ 4 Change to Table 4, Introductory Text ............................................ 5 Change to Table 7, Introductory Text ............................................ 6 Changes to Figure 29, Figure 31, and Figure 32 ......................... 30 Changes to Ordering Guide .......................................................... 31 4/07Revision 0: Initial Version Rev. B Page 2 of 32 OBSOLETE