2.5 V to 5.5 V, 500 A, 2-Wire Interface
Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305/AD5315/AD5325
FEATURES GENERAL DESCRIPTION
AD5305: 4 buffered 8-bit DACs in 10-lead MSOP 1
The AD5305/AD5315/AD5325 are quad 8-, 10-, and 12-bit
A version: 1 LSB INL, B version: 0.625 LSB INL
buffered voltage output DACs in a 10-lead MSOP that operate
AD5315: 4 buffered 10-bit DACs in 10-lead MSOP
from a single 2.5 V to 5.5 V supply, consuming 500 A at 3 V.
A version: 4 LSB INL, B version: 2.5 LSB INL
Their on-chip output amplifiers allow rail-to-rail output swing
AD5325: 4 buffered 12-bit DACs in 10-lead MSOP
with a slew rate of 0.7 V/s. A 2-wire serial interface that
A version: 16 LSB INL, B version: 10 LSB INL
operates at clock rates up to 400 kHz is used. This interface is
Low power operation: 500 A @ 3 V, 600 A @ 5 V
SMBus compatible at V < 3.6 V. Multiple devices can be
DD
2
2-wire (I C-compatible) serial interface
placed on the same bus.
2.5 V to 5.5 V power supply
The references for the four DACs are derived from one
Guaranteed monotonic by design over all codes
reference pin. The outputs of all DACs can be updated
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
simultaneously using the software LDAC function.
Three power-down modes
Double-buffered input logic
The parts incorporate a power-on reset circuit, which ensures
Output range: 0 V to VREF
that the DAC outputs power up to 0 V and remain there until a
Power-on reset to 0 V
valid write takes place to the device. There is also a software
Simultaneous update of outputs (LDAC function)
clear function to reset all input and DAC registers to 0 V. The
Software clear facility
parts contain a power-down feature that reduces the current
Data readback facility
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
On-chip rail-to-rail output buffer amplifiers
The low power consumption of these parts in normal operation
Temperature range: 40C to +105C
makes them ideally suited for portable battery-operated equip-
ment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V,
APPLICATIONS
reducing to 1 W in power-down mode.
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
1
Protected by U.S. Patent No. 5,969,657 and 5,684,481.
Programmable attenuators
Industrial process control
FUNCTIONAL BLOCK DIAGRAM
V
DD REF IN
LDAC
DAC
INPUT
STRING
BUFFER V A
OUT
REGISTER
REGISTER
DAC A
INPUT DAC
SCL STRING
BUFFER V B
OUT
REGISTER
REGISTER
DAC B
INTERFACE
SDA
LOGIC
INPUT DAC
STRING
BUFFER V C
OUT
REGISTER REGISTER
DAC C
A0
INPUT DAC
STRING
V D
BUFFER
OUT
REGISTER REGISTER
DAC D
POWER-DOWN
POWER-ON LOGIC
AD5305/AD5315/AD5325
RESET
GND
Figure 1.
Rev. G
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00930-001AD5305/AD5315/AD5325
TABLE OF CONTENTS
Features .............................................................................................. 1 Read/Write Sequence................................................................. 16
Applications....................................................................................... 1 Pointer Byte Bits ......................................................................... 16
General Description ......................................................................... 1 Input Shift Register .................................................................... 16
Functional Block Diagram .............................................................. 1 Default Readback Condition .................................................... 17
Revision History ............................................................................... 2 Multiple-DAC Write Sequence................................................. 17
Specifications..................................................................................... 3 Multiple-DAC Readback Sequence ......................................... 17
AC Characteristics........................................................................ 5 Write Operation.......................................................................... 17
Timing Characteristics ................................................................ 5 Read Operation........................................................................... 17
Absolute Maximum Ratings............................................................ 7 Double-Buffered Interface ........................................................ 18
ESD Caution.................................................................................. 7 Power-Down Modes .................................................................. 18
Pin Configuration and Function Descriptions............................. 8 Applications..................................................................................... 20
Typical Performance Characteristics ............................................. 9 Typical Application Circuit....................................................... 20
Terminology .................................................................................... 13 Bipolar Operation....................................................................... 20
Functional Description .................................................................. 15 Multiple Devices on One Bus ................................................... 20
Digital-to-Analog Section ......................................................... 15 AD5305/AD5315/AD5325 as a Digitally Programmable
Window Detector....................................................................... 21
Resistor String............................................................................. 15
Coarse and Fine Adjustment Using the
DAC Reference Inputs ............................................................... 15
AD5305/AD5315/AD5325 ....................................................... 21
Output Amplifier........................................................................ 15
Power Supply Decoupling ......................................................... 21
Power-On Reset .......................................................................... 15
Outline Dimensions....................................................................... 23
Serial Interface ............................................................................ 16
Ordering Guide .......................................................................... 23
REVISION HISTORY
Added Octals Section to Table II.................................................. 18
5/06Rev. F to Rev. G
Updated Outline Dimensions....................................................... 19
Updated Format..................................................................Universal
Changes to Ordering Guide .......................................................... 24
4/01Rev. C to Rev. D
Edit to Features Section ....................................................................1
10/04Rev. E to Rev. F
Edit to Figure 6 ..................................................................................1
Changes to Figure 6........................................................................ 11
Edits to Right/Left and Double Sections
Changes to Pointer Byte Bits Section........................................... 12
of Pointer Byte Bits Section........................................................... 11
Changes to Figure 7........................................................................ 12
Edit to Input Shift Register Section.............................................. 12
8/03Rev. D to Rev. E Edit to Multiple-DAC Readback Sequence Section................... 12
Added A Version.................................................................Universal Edits to Figure 7.............................................................................. 12
Changes to Features.......................................................................... 1 Edits to Write Operation section.................................................. 13
Changes to Specifications................................................................ 2 Edits to Figure 8.............................................................................. 13
Changes to Absolute Maximum Ratings ....................................... 5
Edits to Read Operation section................................................... 14
Changes to Ordering Guide ............................................................ 5 Edits to Figure 9.............................................................................. 14
Changes to TPC 21......................................................................... 10 Edits to Power-Down Modes section .......................................... 15
Edits to Figure 12............................................................................ 16
Rev. G | Page 2 of 24