8-Channel, 12-Bit, Configurable ADC/DAC with On-Chip Reference, SPI Interface Data Sheet AD5592R When an I/Ox pin is configured as an analog input, it is FEATURES connected to a 12-bit ADC via an analog multiplexer. The input 8-channel, configurable ADC/DAC/GPIO range of the ADC is 0 V to VREF or 0 V to 2 VREF. The ADC Configurable as any combination of has a total throughput rate of 400 kSPS. The I/Ox pins can also 8 12-bit DAC channels be configured as digital, general-purpose input or output 8 12-bit ADC channels (GPIO) pins. The state of the GPIO pins can be set or read back 8 general-purpose digital input/output pins by accessing the GPIO write data register or the GPIO read Integrated temperature sensor configuration register, respectively, via a serial peripheral SPI interface interface (SPI) write or read operation. Available in 16-ball, 2 mm 2 mm WLCSP The AD5592R/AD5592R-1 have an integrated 2.5 V, 25 ppm/C 16-lead, 3 mm 3 mm LFCSP reference, which is turned off by default, and an integrated 16-lead TSSOP temperature indicator, which gives an indication of the die temperature. The temperature value is read back as part of an APPLICATIONS ADC read sequence. Control and monitoring The AD5592R/AD5592R-1 are available in 16-ball, 2 mm General-purpose analog and digital inputs/outputs 2 mm WLCSP, 16-lead, 3 mm 3 mm LFCSP, and 16-lead GENERAL DESCRIPTION TSSOP. The AD5592R/AD5592R-1 operate over a temperature range of 40C to +105C. The AD5592R/AD5592R-1 have eight I/Ox pins (I/O0 to I/O7) that can be independently configured as digital-to-analog Table 1. Related Products converter (DAC) outputs, analog-to-digital converter (ADC) Part No. Description inputs, digital outputs, or digital inputs. When an I/Ox pin is AD5593R AD5592R equivalent with VLOGIC and RESET pins and configured as an analog output, it is driven by a 12-bit DAC. 2 an I C interface The output range of the DAC is 0 V to V or 0 V to 2 V . REF REF FUNCTIONAL BLOCK DIAGRAM V V DD REF AD5592R 2.5V POWER-ON REFERENCE RESET GPIO0 INPUT DAC DAC 0 SYNC I/O0 REGISTER REGISTER SCLK SDI GPIO7 DAC INPUT SPI SDO I/O7 DAC 7 REGISTER REGISTER INTERFACE LOGIC RESET MUX SEQUENCER 12-BIT SUCCESSIVE T/H APPROXIMATION ADC TEMPERATURE INDICATOR GND Figure 1. AD5592R Functional Block Diagram Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. Tel: 781.329.4700 20142020 Analog Devices, Inc. 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Technical Support AD5592R Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ................................................................................ 26 Applications ...................................................................................... 1 Power-Up Time .......................................................................... 26 General Description ......................................................................... 1 Write Mode ................................................................................. 26 Functional Block Diagram .............................................................. 1 Read Mode .................................................................................. 26 Revision History ............................................................................... 2 Configuring the AD5592R/AD5592R-1 ................................. 27 Functional Block Diagram (AD5592R-1) ...................................... 3 General-Purpose Control Register .......................................... 29 Specifications .................................................................................... 4 DAC Write Operation ............................................................... 30 Timing Characteristics ................................................................ 7 DAC Readback ........................................................................... 31 Absolute Maximum Ratings ........................................................... 9 ADC Operation .......................................................................... 32 Thermal Resistance ...................................................................... 9 GPIO Operation ......................................................................... 36 ESD Caution.................................................................................. 9 Three-State Pins ......................................................................... 38 Pin Configurations and Function Descriptions ......................... 10 85 k Pull -Down Resistor Pins ............................................... 38 Typical Performance Characteristics ........................................... 15 Power-Down Mode ................................................................... 39 Terminology .................................................................................... 20 Reset Function ............................................................................. 40 ADC Terminology ..................................................................... 20 Readback and LDAC Mode Register ......................................... 40 DAC Terminology ..................................................................... 21 Applications Information ............................................................. 42 Theory of Operation ...................................................................... 23 Microprocessor Interfacing ...................................................... 42 DAC Section................................................................................ 23 AD5592R/AD5592R-1 to SPI Interface .................................. 42 ADC Section................................................................................ 24 AD5592R/AD5592R-1 to SPORT Interface ........................... 42 GPIO Section .............................................................................. 25 Layout Guidelines ...................................................................... 42 Internal Reference ...................................................................... 25 Outline Dimensions ....................................................................... 43 RESET Ordering Guide .......................................................................... 44 Function ......................................................................... 25 Temperature Indicator .............................................................. 25 REVISION HISTORY 8/2020Rev. E to Rev. F Changes to ADC Section ............................................................... 24 Changes to Figure 32 ..................................................................... 18 Added Calculating ADC Input Current Section, Table 12, and Figure 39 .......................................................................................... 24 11/2018Rev. D to Rev. E Changes to Temperature Indicator Section ............................... 25 Changes to Temperature Indicator Section ................................ 25 Changes to Table 18 ....................................................................... 28 Changes to Ordering Guide .......................................................... 44 Changes to Table 33 ....................................................................... 36 Changes to Table 39 and Table 41 ............................................... 37 8/2017Rev. C to Rev. D Changes to Ordering Guide .......................................................... 42 Changed VLOGIC Parameter, Table 2 ............................................... 7 Changes to Table 4 ........................................................................... 8 10/2014Rev. 0 to Rev. A Changed V Pin Description, Table 10 .................................. 13 Added 16-Lead TSSOP ...................................................... Universal LOGIC Changed V Pin Description, Table 11 .................................. 14 Changes to Gain Error Table 2 ....................................................... 4 LOGIC Changes to Table 6 ......................................................................... 10 2/2017Rev. B to Rev. C Added Figure 6 and Table 8 .......................................................... 12 Changes to Figure 9 Caption and Table 11 Title ....................... 14 Added Figure 8 and Table 10 ........................................................ 14 Change to D15 Bit Description, Table 22 ................................... 19 Changes to Table 12 ....................................................................... 25 Added Figure 48 Outline Dimensions ....................................... 40 2/2016Rev. A to Rev. B Changes to Ordering Guide .......................................................... 41 Changes to Table 2 and Table 3...................................................... 7 Added Figure 7 and Table 9 Renumbered Sequentially .......... 12 8/2014Revision 0: Initial Version Rev. F Page 2 of 44